Talk:Transactional memory

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How Hardware TM is implemented

Hi, how HTM is implemented by Intel, Sun and other designers? There are some speculations on Intel Haswell implementations, based on work by Kanter (RWT): diff, article1, article2 `a5b (talk) 02:32, 12 November 2013 (UTC)[reply]

Sorry, but didn't you write the Transactional Synchronization Extensions#Implementation section? -- Dsimic (talk) 21:21, 12 November 2013 (UTC)[reply]

I've added a bunch of papers covering the major HTMs. Annoyingly, the Power8 paper gives the least (hardware) details while the EC12 and BG/Q have more. 86.127.138.234 (talk) 04:15, 3 February 2015 (UTC)[reply]

Other Historical Transactional Memory applications

I'm working from a very long-ago series of conversations so I very well could be wrong. In the early 1990s, I worked with a bunch of key engineers from Tandem Computers, who had been there since the founding in the late 1970s. I recall talking about the implementation of the hardware, which was all about fault tolerance and about transaction integrity -- they targeted the banking market obsessively, and ran most of the early ATM networks. I vividly recall one of the key architects of that platform telling me that they had something that sure sounds like the transactional memory described in this article. In their system, application working storage in RAM would roll back, synchronized with a rollback of a failed database transaction, so that the developer would not have to worry about application state being out of sync with the database. I'm no longer an engineer and haven't talked to these people in 25+ years, but it might be worth checking out to see if I'm correct and thus that Tandem deserves mention as an early pioneer in this field. Note that I'm not tooting my own horn as I never worked for Tandem or in their software vendor ecosystem. — Preceding unsigned comment added by 12.9.88.204 (talk) 18:57, 15 March 2019 (UTC)[reply]