Talk:Flash memory/Archive 1

Archive 1

Lifespan explanation

So what exactly happens to the cells over time that gives them a limited lifespan? --Dtcdthingy 09:35, 25 Apr 2005 (UTC)

The Flash memory Floating gate acts as the charge storage electrode for the cell. However, due to repeated stresses on the tunneling oxide due to read/write cycles and interface oxide trap generation, charge leakage occurs causing difficulties in data retention.--Abahuguna 22:59, 18 August 2005 (UTC)

write / erase cycles stress the tunneling oxide. This stress causes trap generation in the oxide. Traps generated in the tunneling oxide degrade charge storage properties of a flash cell. This limits number of write / erase operation (or the lifespan) for a flash cell.

mlc vs slc

some discussion on Multi level cell and Single level cell flash technologies would be nice.

AFAIK:

• MLC is used in photo memory sticks (and USB sticks) and is cheaper, but slower, with 10,000 read/write cycles. (used by Toshiba, among others.
• SLC is used in USB sticks and is more costly, but faster, with 100,000 read/write cycles. (used by Samsung, among others.)

• Since my last posting I have been told that these 10,000/100,000 figures are conservative lifetime guarantees by the flash manufacturers. Typical lifetime is an order of magnitude higher (i.e. 100,000/1,000,000)

Brewthatistrue 23:10, 18 August 2005 (UTC)

• MLC need robust correction code because more that one bit error can happen. This mean hardware implementation of the ecc, or more cpu cycle need for the software algorithm.

• In MLC you can only write once data in a block before errasing it (NOP = Number of Program). For SLC NOP is small but often NOP >=2.

See also: Memorynet Discussion on MLC vs SLC

Read Only access Lifetime?

Missing from the lifespan explanation is how long data that is written once (e.g. like a write once CD) will last. I have a vague recollection of seeing a figure of 10 years. Also, given these two scenarios:

• write once, read frequently (e.g. read multiple times a day)
• write once, read extremely rarely (e.g. once every 5 years)

is the expected life the same or different for these scenarios?

Will data stored on flash like this last longer or shorter than data stored on CD-Rs and DVD-Rs? Funkyj 22:04, 30 September 2005 (UTC)

Good question. How long will the Flash survive without power? Does it need to be refreshed in intervals? Is a Flash-operated MP3 player a good candidate for a time capsule? -- Syzygy 11:43, 20 December 2005 (UTC)

long term data endurance is probablly in the low decades regardless of read activity Plugwash 12:34, 14 June 2006 (UTC)

For something as widely used as flash I'm sure that the people who design and build flash memory have definitive answers (e.g. answers that don't include the word probably) to these questions. It is a little surprising that we can't find one of them to help us out. Funkyj 22:50, 15 June 2006 (UTC)

Well the last microcontroller data sheet i looked at said an expected lifetime of 20 years, i don't know if standalone flash is better or worse though. The issue is that the insulators in the floating gates are not perfect and so the charge in the gates slowly leaks away. Plugwash 23:00, 15 June 2006 (UTC)

Leakage of electrons from the floating gate is what would affect data retention, therefore calculations of data life must account for the storage temperature. I believe that measurements of data life are done at a high temperature and then the appropriate thermodynamic equation is used to refer back to 'normal' (300K) temperatures. 88.96.204.222 09:41, 1 March 2007 (UTC) MikeW

Electron leakage (off the floating gate) is the primary limiter of data retention. It is temperature dependent, and since it's obviously unrealistic to leave a product sitting on a shelf for 10 years before advertising a retention spec, the measurements are made at high temperatures and adjusted back to expected lifetime at room temperature. Since longer is better, verifying the advertised numbers is difficult at best, and no common use scenario actually exploits the limits of that specification, there's a fair amount of marketing hype in the figures advertised on most data sheets.

Better data retention can be obtained at the cost of program performance (i.e. doing a better job of programming takes more time). To work around this, some companies now offer two-stage programming. Data written with a fast initial program is guaranteed for a month or so. To guarantee the full 10-year (or however long) retention, the data must be refreshed sometime within that first month. The refresh presumably occurs (maybe in the background) when it's non-time-critical. During refresh, program performance isn't an issue, so the program algorithm can take the time necessary to do a good job programming, providing better retention. Fhaigia (talk) 05:25, 16 August 2008 (UTC)

Flash lifetime, really?

What affects flash lifetime, really? I would envision that flash would last a very long time typically, due to wear leveling especially. Consider the following layouts:

--[CtlChip]--[256M]

Fig. A 256M CompactFlash drive.

--[CtlChip]--[256M]
           \-[256M]

Fig. B 512M USB Flash drive.

           /-[1.00G]
--[CtlChip]--[1.00G]-[1.00G]
           \-[1.00G]

Fig. C iPod nano.

--[CtlChip]--16x[2.00G]

Fig. D Samsung 32GB laptop flash 'hard drive'.

An easy metric is the unrealistic assumption that we will average writing to one block per one second. Assuming that all devices use wear leveling implemented in the CtlChip, and all storage chips are NAND with 1,000,000 writes and 64K blocks, lifetime in years is calculated as:

$(10.0^{6}xC/64.0K)/(60x60x24.0x365.25)$

Or, spatially, where C = capacity and W = writes (blocks written to):

$(Cx10.0^{6}bytesx((64.0x1024bytes)/Wblocks))/(60s/minx60min/hrx24.0hr/dayx365.25day/yr)$

This gives the units in years over block-seconds:

$year/blocksecond$

For values of one blocksecond, one year/blocksecond is equivalent to one year of life. Writing to more than one block per second shortens life; writing to less extends it. Lifetime is calculated by ((year/blocksecond) * blocksecond). Therefor, the following lifetimes can be calculated:

• Fig. A: 130 years
• Fig. B: 260 years
• Fig. C: 2080 years
• Fig. D: 16600 years

Systems with low available main memory may occasionally swap thrash attempting this; but at least on Linux swap when paged in is left in the swap file and not re-written if it is not changed. By this we could say that a multi-terrabyte data array (ignore that it's cost-prohibitive) would last practically forever (520,000 years per blocksecond).

I do not know how scalable current wear leveling algorithms are; however, a hierarchial approach where wear is dealt with in multiple levels would likely be scalable enough as capacity increased. I believe this is log(n) in terms of complexity vs size but I'm not a systems analyst.

             /-[W3aa]--[NAND]
      /-[W2a]--[W3ab]--[NAND]
--[W1]
      \-[W2b]--[W3ba]--[NAND]
             \-[W3bb]--[NAND]

Each CtlChip at W3 would manage wear on the attached NAND chip(s) and report average (or total if you wish) wear across those chips. At W2, each CtlChip would manage wear across the W3 chips connected to it, favoring writes on the W3 chip with more average wear; and report average wear across its W3 chips. At W1, wear is analyzed across W2 chips and balanced appropriately as was done at W2.

To make this work, each level would have to be able to read into lower levels and ask about re-mapping of physical blocks. Thus when W2a decides W3ab has too much wear and wants to move a page to physically map on W3aa, it would send the re-mapping to W3ab; read the current contents from W3ab; alter the contents as they would be anyway; and write out to the new area on W3aa. When reading, W2a would be reported to by W3ab that the data is on W3aa, of course.

The strength in this particular re-mapping scheme is that the control chips closer to the NAND handle remapping as much as possible, allowing W1 to avoid maintaining and processing a full re-mapping table, and also shortening paths for near-look remapping. In this scheme, no single level is capable of truly arranging the stored data into its contiguous view; but process through each level naturally reconstructs the contiguous state anyway.

As a final word, there is no need to ACTUALLY have multiple CtlChips; this would likely INCREASE complexity. My assumption is that the algorithm would be a processed mathematical formula, since that is what an algorithm is. Using the above as a logical view, the algorithm could run against each block as it is modified; thusly, a full recalculation of wear distribution could be avoided without the use and scanning of a huge table. The gains from this may be insignificant; I just felt like babbling really ;)

1's or 0's?

The article says:

To erase (reset to all 1's, in preparation for reprogramming) a NOR flash cell, a large voltage differential is placed between the CG and source, which pulls the electrons off through quantum tunneling.

Shouldn't it say "reset to all 0's" instead of "1's"? Spikey 16:54, 26 June 2006 (UTC)

No, the default state of a single-level flash memory cell is considered to be a logic 1. In this state, the floating gate has no charge on it, and thus the memory cell acts like a normal MOSFET. When the control gate is activated via the word line (used to select a particular memory location), the channel of the MOSFET is conducting, equivalent to a closed switch. Customarily, the closed-switch state of a MOSFET is considered equivalent to a logic 1. MOXFYRE (contrib) 18:34, 13 May 2007 (UTC)

Capacity

I moved these comments here from the main article --Thalakan 15:37, 21 June 2006 (UTC)

Question validity, probally should be gigabit. Recommend changing gigabit to more popular gigabyte and correcting the values as well. Gigabit affiliated with communications (where as Gigabyte is affiliated with data storage) and errors such as these occuring due to misunderstanding of what is being said. Also recommend if assumption is true to remove the line saying "and later...memory chip" as second sentence appears to be relating to that.

Further more, as a note. The article that 'appears' the be refrenced does NOT say they created a 32 GB chip but rather put together an assortment of such chips to create a Flash HD of that size

This article really needs a chart of capacities. These memory cards are sold as 1Gb (for example) but are only really around 900 Mb. -- jp

---

I recommend also using unambiguous Kibibit/byte, Mebibit/byte, Gibibit/byte scales instead of the more indeterminate kiobit/byte, megabit/byte and gigabit/byte.

-- mhg 18-Dec-2006

---

EEPROM

Also, EEPROMs use a totally different principle than flash. The ability to erase single bytes is actually an advantage and requires additional effort.

Additional mentioning of multilevel flash and mirror bit/NROM might be adequate --Qdr 11:00, 16 Jul 2004 (UTC)

What are the limits on the number of cycles you can expect from a flash device ?

Redundant word in article?

"In NOR flash, each cell looks similar to a standard MOSFET transistor, except that it has two gates instead of just one."

Just me being pedantic, but isn't "MOSFET transistor" redundant - like the PIN number syndrome seeing as the "T" in "MOSFET" stands for transistor? Best to remove it or am I just being OTT?

Whilst it may be redundant logically, most people don't know what a MOSFET is, or what it stands for. boffy_b 15:51, 2005 Apr 2 (UTC)

Perhaps it should be "...similar to a standard MOSFET (metal oxide semiconductor field-effect transistor), except..."

I would simply use "MOSFET" without any redundant duplication of words that are already part of the acronym. "MOSFET" could then be wikified, so that readers who are unfamiliar with the term can educate themselves. There is no need for redundancy in a hyperlinked document that most people will read on-line. Brolin Empey 22:31, 12 May 2006 (UTC)

See RAS syndrome for why we say things like ATM machine, PIN number, FET transistor, and HIV virus, and why this may actually be good thing even though it's redundant :-) MOXFYRE (contrib) 18:36, 13 May 2007 (UTC)

Booting

Can anybody write a section about booting flash memory ?? (from the BIOS).

Why not make a redirection or link to this article: http://en.wikipedia.org/wiki/Booting You do not 'boot' or booting flash memory, but rather you boot a PC or Computer from flash memory or whatever. And the BIOS http://en.wikipedia.org/wiki/Bios has to support it. Ootje van Kampen

As far as I know, it's less about the media being booted and more about the interface. What I mean is: it's not booting from a flash drive that's the issue, it's the fact that it's connected using USB. I imagine you could (somehow) hook up a flash drive to an IDE interface and the BIOS wouldn't know any better - it just talks IDE/USB etc and doesn't care what's past the interface. I could be wrong... StephenFalken 08:25, 16 April 2006 (UTC)

And indeed you can. CompactFlash IDE and ISA are all essentially the same thing, and you can plug one into the other with mostly passive componentry. CompactFlash/IDE adaptors go for a few quid on ebay, and sure enough, the computer can't tell it's booting off a CF card.

That's right, CompactFlash is basically just IDE with a different pinout. However, it's important to note that while all hard drives today support fast DMA transfers, many cheaper CompactFlash cards only support PIO mode... which is muuuuuch slower for data transfer. Not so much of an issue for cards that are just used to read and occasionally write songs and photos, but will be a huge bottleneck if you want to run a database server off a CF card ;-) ǝɹʎℲxoɯ (contrib) 20:28, 19 November 2007 (UTC)

Performance

It is difficult to find much information about the performance of flash memory. A section on this topic would be nice.

Actually, it's very easy to find out everything you could want to know about the performance of a particular flash memory chip. All flash memory manufacturers ( [Atmel], [Micron], Altera, AMD], Intel, Toshiba, Samsung ... and some I'm forgetting) put complete data sheets on their web site. But data sheets are far too detailed to simply copy-and-paste into an encyclopedia. (FIXME: move this list of flash memory manufacturers to the article). --DavidCary 12:40, 22 July 2005 (UTC)

[FAQ: How long does it take to program a byte or a sector of data?]

Could someone give some estimates, though? Say, 'compared to typical 7200 rpm harddrive...', or some such comparison. I'm also wondering if flash would give any advantages if it were integrated into the memory hierarchy and used as a cache for swapping to hd (the price is in the right place now , it seems, for 1-2GB flash memories installed in the system). --24.55.70.103 12:47, 19 July 2006 (UTC)

• I believe that that kind of data is hard to generalize. It seems that it is pretty much dependent on the implementation. I have a USB 2.0 flash thumb drive which has some nice speeds but on the other hand I have a couple of SD cards which are a bit disappointing. If that wasn't enough, the performance that I get from my cards also vary. To make matters worse, I can get transfer speeds from virtually zero to 14MB/s from the same exact flash card. With the data varying to much It would be rather pointless to try to give an exact value, unless you find something like "240 MB/s +- 240MB/s" a useful value --Mecanismo | Talk 09:33, 21 June 2007 (UTC)

• Read vs. write is also interesting: Random access read should be always quite fast (no seeks), but random access write still needs to do a read-modify-write cycle for a complete erase block (May depend on how the wear level algorithm works) and this can slow writes down a lot. I have a Transcend MLC 16GB flash with a normal ext3 filesystem on it and it often slows down to a crawl on writes (especially if cache flushes (fsync/msync) are involved). Maybe it's just a crappy wear leveling algorithm, maybe this is a more general problem? Ranma (talk) 17:35, 5 March 2008 (UTC)

• Program times will be quite different between NAND and NOR, and between SLC and MLC. (Applications that require fast programming are one reason why SLC Flash is still available.) If you're looking to compare to a hard drive, look at datasheets from some of the manufacturers mentioned above for their highest-density NAND MLC Flash devices. NAND MLC Flash is the only type of Flash used in SSDs right now, because anything else would be too expensive (and even MLC NAND is pretty spendy compared to spinning platters). Fhaigia (talk) 05:57, 16 August 2008 (UTC)

The above FAQ link doesn't work. Use this instead link title —Preceding unsigned comment added by 60.241.12.136 (talk) 07:26, 3 October 2009 (UTC)

I tried but could not find datasheets to answer the question "How long does an erase last typically?". I know there is no general exact answer, but is it 1 microsecond? nanosecond? millisecond? 10 ms? I mean the types used for storage, like USB flash drives and SSD. Thanks. --Xerces8 (talk) 13:24, 3 December 2009 (UTC)

OK, I found that data, but stupid me, forgot to note them. I will "refind" it and post the results here... --Xerces8 (talk) 12:42, 22 December 2009 (UTC)

Standards

Can any one write a section about flash memory standards and standards competition among flash memory manufacturers?

• not quite there, but possibly a start. see the mlc vs slc heading below. Brewthatistrue 21:22, 24 Jun 2005 (UTC)

• I'm not sure what kind of standards you're looking for, but JEDEC defines most of the standards applicable to Flash. Fhaigia (talk) 05:59, 16 August 2008 (UTC)

Fragility of data

A section would be nice talking about the fragility (or lack of it) of flash memory. What happens if you stick it to a refrigerator with a magnet? Bring it into a big electrical field of some kind? Tempshill 00:29, 27 May 2005 (UTC)

it should be pretty much the same as eprom or eeprom. basically anything that makes silcon dioxide conduct and that can get through the packaging will do it. magnets shouldn't have any effect not sure about electric fields but i'd imagine they would have to be pretty damn big to have any effect.

UV would erase flash if it could get to the chip but it generally can't get through the chip package. x-rays or gamma rays would do it, not sure how much would be needed to cause actual data loss though. static shocks could damage a bare flash chip easilly but are unlikely to be much of an issue inside something like a keydrive. Plugwash 00:38, 27 May 2005 (UTC)

I've personally scrubbed my USB flash drive with the most powerful magnet I have available (pulled from an old microwave). My diff tools show that the data in my flash is still identical to my backup copy on my hard drive. Since flash is completely immune to my powerful magnetron magnet, your wimpy refrigerator magnets will also be harmless. --DavidCary 12:40, 22 July 2005 (UTC)

Is there a single time programmable ROM?

Hi,

I wonder if there is a single time programmable ROM availble.

if there is, how is its cost in comparing with flash memory? and for how long would data can be stored on it without having errors?

thanks,

Yuval.

There are two forms of OTP memory afaict. One is windowless EPROM, this can be erased but only with great difficulty (x-rays will generally do it) the other is fuselink prom but i don't think either is easillly availible in the large almost disk like sizes that flash is. Plugwash 17:24, 6 October 2005 (UTC)

Fusible-link PROM was one-time programmable. It's obsolete, with the possible exception of military products. In the 1970s, manufacturers would supply factory-programmed EPROMs in windowless packages for verification or preproduction before a masked ROM was ready (e.g., Intel 1602, 2608). Initially they didn't provide unprogrammed EPROMs in windowless packages due to the inability to test them after packaging. True OTP EPROMs became available in the mid-1980s.

Today the use of OTP memory is typically not cost-effective except in specialized high-volume applications; flash memory is manufactured in such high volume that the cost per bit is often better than OTP parts and nearly as good as masked ROM.

Note that windowless EPROMs *cannot* be erased by x-ray exposure; very high levels of x-ray exposure will damage the part long before any effective erasure occurs.

Traditionally EPROM data retention (including OTP parts) was specified as a minimum of ten years. It is now common for flash memory parts to have much longer specified data retention. --Brouhaha 01:42, 7 October 2005 (UTC)

i've heared of people successfully erasing some chips with onboard eprom that weren't easilly availible in windowsed packages using x-rays, i guess the feasiblity depends on the exact design of the part. i don't have the details handy though.

You could also just get a CD/DVD burner. CD-Rs and DVD-Rs are technically ROM, but they can only be written once. :P -- trlkly 11:28, 5 December 2007 (UTC)

Sure, there have been "friend-of-friend" stories about that circulating on the internet for years. But the physics of it don't work. The wavelength of x-rays isn't even close to what it takes to cause the charge to leak through the oxide. If it worked, they would have sold it as a feature. --Brouhaha 22:23, 7 October 2005 (UTC)

"Standards question!"

As off late 2005. Do you think there's a dominant design/standards in the flash memory market? Is there a dominant player (SanDisk, may be?) in the market? or the battle for the dominant design is still going on, and no single company has its design chosen as the dominant design yet?

There are basically three common interfaces for Flash memory chips, depending on whether they are parallel NOR, serial NOR (SPI), or parallel NAND. Product engineers choose the interface that best fits their application, and for a given interface and capacity there is nearly always a choice between multiple vendors that make footprint-compatible parts. --Brouhaha 18:04, 20 November 2005 (UTC)

i want the electornic circiut of usb flash memory you can send it in newslater@gmail.com

Can flash memory be erased by magnetism?

My teacher said his flash drive was erased because he left it on top of his cell phone overnight. Is this possible? Twilight Realm 02:02, 4 January 2006 (UTC)

That's funny because cell phones have flash memory chips in them. 01:42, 20 January 2006 (UTC)

I know of a manufacturer who builds in X-ray shielding, so there are things that can cause data loss if not compensated for. I don't know if magnetism is one of them. 71.103.109.60 22:24, 13 February 2006 (UTC)

see also: busting the biggest computer myths: magnets zap your data

Principles of operation

This section is a little unclear to me regarding programming and erasing. Am I correct in assuming that during programming a high positive voltage on CG attracts electrons from the channel to the FG. During an erase is it an even higher voltage to move them from the FG onto the CG? If so why is one process hot-electron injection and the other quantum tunneling as both seem to be moving electrons through the insulating gate oxide by an electric field? Or am I misunderstanding something?

A simple diagram would help.

• Yes, programming puts a high voltage on the CG, and a slightly lower voltage on the drain. Electrons travel from the source, at a low voltage (usually ground), through the substrate toward the drain. The drain voltage causes the electrons to accelerate and move very rapidly. The potential on the CG then draws the electrons upward, crashing through the oxide onto the FG. To get through the oxide, the electrons have to be moving at a good clip ("hot"), hence the term hot-electron injection.

Erasure is the opposite. Electrons are not pulled up into the CG. The oxide used over the FG is usually designed to make this very difficult, so electrons that manage to get through the oxide between the substrate and floating gate won't keep right on going through the oxide between the floating gate and control gate. (They'd be wasted if they didn't stay on the FG.) Instead, to erase, electrons are pulled back down from the FG into the source by floating the drain, putting a very low (i.e. negative) voltage on the CG, and a positive voltage on the source. Electrons all run over to the source side of the FG then pass through the oxide by tunneling (on account of the large potential difference between the source and the CG).

Hot electron injection and erasure tunneling are given different names because the mechanism of electron movement through the oxide is different in each case. Tunneling isn't used for programming, among other reasons, because it's too slow. Fhaigia (talk) 06:27, 16 August 2008 (UTC)

NOR and NAND types

SmartMedia and Compact Flashes are NAND Type Memory but not NOR type as mentioned by you. Please verify this and update the page.

Dunno who posted that comment. I found it above the page index so moved it here. Anyway, I'd like to know what the acronyms stand for. I don't think they are NOR nor NAND logic gates (as referenced by the EEPROM flash page) but I can't find any suggestion as to how the letters were derived. --Ikester 19:29, 1 March 2006 (UTC)

this is weird: i'm an electrical engineer, i fully understand Boolean logic, truth tables, AND, OR, NOT, NAND, NOR, XOR, XNOR, combinatoric logic, Karnaugh maps, race hazards, flip-flops, state machines, a bit about TTL and MOS (and CMOS) circuitry, but i do not understand what building flash memories out of NAND logic has anything to do with the fact that they "cannot provide execute-in-place". what do the two have to do with each other?? there is no reason that NAND logic "cannot provide execute-in-place" any less or any more than NOR logic. as far as the logic function goes, because of De Morgan's laws, anything done with NOR can be done with NAND. it's just the conjugate logic.

There's no fundamental reason why a flash memory with NAND cells couldn't allow random access to individual bytes. However, the original goal of NAND flash was to reduce the number of transistors needed to implement a given memory capacity. One way to do this is to use a NAND-gate like memory cell rather than a NOR-gate like cell (see section 2.1 of Toshiba's NAND design guide). Another way to reduce the device complexity is to get rid of the dedicated external address lines of NOR flash; Toshiba made this change as well when they came up with NAND flash. Basically, NAND flash can't do random-access because the interface doesn't support it... in the same way that hard disks interfaces only allow reading/writing in one-sector chunks. I'll try to figure out where to incorporate this info into the article. MOXFYRE (contrib) 20:58, 10 May 2007 (UTC)

the reason that these USB flash memories do not execute in place is that they are peripheral devices that the CPU accesses only through the USB driver software (or firmware) and hardware. it doesn't matter how the external flash is constructed inside, like a hard disk or some other magnetic media, you will always have to download the data in blocks into the computer RAM before you can execute it. why is this statement in there? i find it only confusing and either the person writing it is a dilettante or i am. if it's the latter, i wouldn't mind someone explaining it to me. Rbj 02:34, 22 April 2006 (UTC)

Gaurav Mehta== 12/15/2006 == In the penultimate paragraph of this article are a number of statements that are related to present time. Are these statements valid as of 2005, 2006? If so, I think this is a place where a [[as of 2006]] link needs to go. -- llywrch 16:20, 21 March 2006 (UTC)

The NAND memory and NOR memory get their name because of the architecture they have. The Structure of the cells in the NAND memory resembles NAND and the structure of the cells in the NOR Memory resembles NOR. I know this because I read a paper written by a guy working in Intel so I would want to add some credibility to his knowledge.

Check out this link: www.mrs.org/s_mrs/bin.asp?CID=2687&DID=61873&DOC=FILE.PDF

The first paragrah on the third page mentions a line about the confusion that you have

NAND does not support XIP because the interface required to read or write is complex. Reads and writes can only occur in large chunks beginning on fixed address boundaries. This is a side effect of the series architecture of NAND. NOR allows reads and programs to/from random addresses, and has an interface similar to RAM memory, which is the key to allowing XIP operation. (NOR still has to be erased block-by-block.)

Because of the cost-per-bit difference between NAND (cheaper) and NOR, "managed NAND" is now appearing in the market. In such devices, a microcontroller and RAM cache memory are included in the NAND memory. These manage access to the raw NAND memory, hiding the complexity of read/write operations and providing an external interface that offers random-access reads and writes, more like a traditional RAM memory.

The names "NAND" and "NOR" do indeed come from their resemblance to textbook CMOS NAND and NOR gates, respectively. Fhaigia (talk) 06:52, 16 August 2008 (UTC)

Accessing

Is there a way to access the flash memory on my mp3 player to explore it?

There must be! Else how could you load music onto it. Of course, it may require a different software tool than you are using.

Atlant 16:11, 29 March 2006 (UTC)

What kind of software? My mp3 player has a harddrive that is formatted in FAT, but it uses flash memory for upgrading the firmware, etc.

Anyone?

If it's a hard drive player, then you almost certainly can't access the flash yourself. All it would have in it anyway is the firmware, so it wouldn't be too interesting. Assuming that the firmware upgrade files aren't encrypted, you can just download a firmware upgrade, and what you see inside the file will be very similar to what's in the flash. -- DImfeld 01:34, 13 June 2006 (UTC)

Strangely-placed sentences

I removed this sentence from the 'Limitations' section:

The Tungsten T5 PDA and Treo 650 smartphone from PalmOne, released in late 2004, use NAND flash to back up the contents of main memory during normal operations. PalmOne names this technique "non-volatile file system" (NVFS). It gives the illusion of a RAM storage pool that does not lose any of its data when power is removed. This PalmOne knowledge base article explains how this technique works on the Treo 650.

I don't see how it's a limitation.

I removed this sentence from the 'Flash file systems' section:

A special issue is flash memory booting.

I'd have expanded it myself, but I'm not sure what it's trying to say...

StephenFalken 08:27, 16 April 2006 (UTC)

MMU not required for NOR code execution

I fixed this paragraph; an MMU isn't required. Here are some examples from products I've hacked:

this camera copies all code to SDRAM

this camera uses a home-grown software-only paging system to load one of 16 pages into memory before executing. Each page does a specific, related task (example:image compression). One page (with the copying code) stays in memory at all times.

Morcheeba 01:26, 24 May 2006 (UTC)

physical cell structure and origin of the terms nand and nor

does anyone have any information on this? i'd imagine its some relation to nand and nor gates but nand and nor gates are complementry while this article makes out nand and nor flash to be very different. Plugwash 00:28, 20 July 2006 (UTC)

see section 2.1 of the Toshiba NAND design guide and my longer answer to a similar question below. I'd like to incorporate this info into the article since it's a common source of confusion. MOXFYRE (contrib) 21:02, 10 May 2007 (UTC)

I don't understand

Can we get an oversimplified teletubbie freindly explaination? Like 'It stores static electricity on a spot if the bit is 1, and none if it is 0, and there are millions of spots'. Skip the NAND gate electrical engineering degree stuff and introduce it like you would to a kid.

I suggest moving most of the technical terms out of the summary and into the body. Most of the information currently in the summary should be moved to the "Overview" section.

The summary should simply explain that flash memory is non-volatile, solid-state storage. I'm unsure whether to make a brief comparison to non-solid state electronics (spinning hard drives) here or only in the body. Thoughts? 71.103.114.85 21:18, 22 September 2006 (UTC)

Hybrid drives

The article needs a dedicated section explaining the ways in which flash memory is used, and it would be proper to include a brief description of hybrid drive. -User:FrostyBytes 10:29, 20 October 2006 (UTC)

Price trends

I am finding it very difficult to find historical data on average "price per megabyte" for NAND flash chips. This data is reported every week in business news sources, but I can't find a (free, i.e. not iSuppli or inSpectrum) source for a compilation of the last 5 to 10 years. Anecdotes say prices are falling 40 percent per year, but where's the data?Anthony717 23:43, 19 November 2006 (UTC)

NANDs go down by 40% every year. This article probably contains useful links http://www.embedded.com/rss/showArticle.jhtml?articleID=197003257&cid=RSSfeed_embedded_news larytet

ONFI Specification

Has there been any evolution in the specification? The article says results were expected to be available fall 2006. Maybe that info should be updated? Asymmetric 09:55, 6 January 2007 (UTC)

SD card versus USB flash memory

These seem to be competing forms of memory storage. Am I correct? What if any significant advantages/disadvantages exist between them? Tmangray 04:01, 12 February 2007 (UTC)

I think SD is more a form factor than an actual storage technology. However, solid state SD cards use flash memory just as USB thumb drives do. It's merely a matter of the interface. -- mattb @ 2007-02-12T04:42Z

SD also uses a proprietary transfer protocol (while USB flash drives use UMS) and the standard includes some form of DRM copy protection. --Bk0 (Talk)

I was aware that both use flash memory. The last comment is closer to what I'm getting at, but it needs to be simplified and put in practical terms. For instance, why would an individual purchase one form over the other? Am I correct in thinking that the SD card, since it's specially formatted, is less universal than a USB flash memory device? Tmangray 16:48, 12 February 2007 (UTC)

USB flash sticks are primerally intended for moving data between PCs, thier primary advantage is they can be plugged into almost any PC with no adaptors. The various card formats are mostly used in cameras and similar devices where the card fits inside and the end user (once they have picked thier camera) has no choice about what card format to use. Plugwash 17:23, 12 February 2007 (UTC)

NOR and NAND: why those names?

Which technical details are responsible for calling NOR and NAND flash by their respective names? -- 85.182.123.225 18:05, 3 March 2007 (UTC)

NOR and NAND in this context mean that the flash uses NOR gates or NAND gates. I can't provide any details beyond that. -Ravedave 18:43, 3 March 2007 (UTC)

Not exactly. There *is* a reason that NOR and NAND flash are called those names. Basically, NOR cells are arranged in parallel, so that if *any one* of their word lines goes high, the shared bit line goes low (like a NOR gate, one input high => output low). On the other hand, NAND cells are arranged in series, so that only if *all* of their word lines go high, the shared bit line goes low (like a NAND gate, all inputs must be high => output low). This article doesn't explain it at all, but section 2 of Toshiba's NAND Design Guide explains it very well. Can someone figure out where this distinction should go in the article? MOXFYRE (contrib) 20:51, 10 May 2007 (UTC)

NOR and NAND have same device cell however they need to be separated in this article because they have

– different design (explain the names)

– NOR array (cf logic design) for NOR

– NAND array (cf logic design) for NAND

– different operating mode

– channel hot electron programming and electron tunneling erasing for NOR

– electron tunneling for programming and erasing operation in NAND

– And thus they have different properties

– fast read, low parallelism for programming & erasing, low density for NOR

– slow read, high parallelism for programming & erasing, high density for NAND

– And so are used for different purpose

– code storage for NOR

– data storage for NAND

– And so are sold by different industrial

– Spansion, Intel, Samsung, ST, ... for NOR

– Samsung, Toshiba, Hynix, Micron, Intel, ... for NAND

Nevertheless the scheme of the NOR in the article is not correct as it a split gate NOR device and not a standart one. —Preceding unsigned comment added by 83.201.20.127 (talk) 14:32, 26 October 2008 (UTC)

Hmm, I think this is somewhat confused. NAND flash is wired in parallel and accesses are sequential - a discussion of "parallelism" will always be misleading since that carries different connotations in computing. The dual gate FETs are used in both technologies and are essentially an implementation detail - it certainly doesn't change either a NAND or a NOR gate into anything else.

There is no fundamental reason why one or the other should be preferred for either code or data - it depends on more specific requirements. The difference between the two is basically a trade off between desirable factors - NOR is the faster technology whereas NAND has better density, meaning lower cost and the possibility of greater capacity with any given technology. CrispMuncher (talk) 22:16, 26 October 2008 (UTC)

Recent changes

I've made a bunch of recent changes to the article, especially a new section on understanding the distinction between NOR and NAND flash, since this talk page has expressed a lot of confusion on this issue. I'd appreciate any comments on the usefulness of these changes. In particular, I'm wondering if there's a way to consolidate the sections that distinguish NAND and NOR flash into one larger section. Thanks. MOXFYRE (contrib) 18:41, 13 May 2007 (UTC)

Text regarding writes to NOR

In article version dated 5/21/07:

Under heading "NOR Flash"

The erase operation can only be performed on a block-wise basis, that is all the cells in an erase segment must be erased together. Programming of NOR cells, however, can generally be performed one byte or word at a time.

Under heading "Limitations"

... once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but cannot offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written value's.

Taken as a whole, it's clear what this means. In isolation, the text under "NOR Flash" is misleading. A casual reader might conclude that the erase operation provides a quick method for clearing a block, but it is equally possible to "program" all-1s to each individual byte. Should this text be modified with a reference to the Limitations section? Ged Davies 19:14, 22 May 2007 (UTC)

I'm not sure to what extent this is really a problem... the article makes clear that programming means "setting to logical 0" in the context of flash memory. Maybe it could be clarified by changing the first passage you listed to:

The erase operation (setting bits to logical 1) can only be performed on a block-wise basis, that is all the cells in an erase segment must be erased together. Programming of NOR cells (setting bits to logical 0), however, can generally be performed one byte or word at a time.

Or maybe there's a more elegant/less parenthetical way to clarify it? MOXFYRE (contrib) 19:24, 22 May 2007 (UTC)

EEPROM or RAM?

Is flash memory ROM or RAM? EEPROM wikipage shows Flash memory as a kind of EEPROM (thus ROM). But NVRAM article says memory is Non-volatile RAM. Which one is it?

• Flash is based on EEPROM technology. It evolved out of a series of refinements of "reprogrammable ROM" technology. Of course, it is not "read-only memory" in the strict definition since it's explicitly defined to allow data to be modified. It is definitely *not* RAM, since RAM is Random-access memory and many forms of flash (especially NAND) don't allow random/memory-mapped data access. NVRAM is not a very well-defined term... in my experience it most frequently refers to ordinary static RAM with battery backup. I think the NVRAM article is extremely misleading in suggesting that Flash is often considered to be a type of NVRAM.  :-( MOXFYRE (contrib) 03:10, 31 May 2007 (UTC)

Submersion in water?

The article claims flash memory can be submerged in water safely, however the source ( source # 1 ) makes no mention of this.

That's true, the source doesn't back it up, though it does allude to the durability of flash-based devices in other respects. Ppersonally, I have put USB flash drives and SD cards through the wash and dryer, with no ill effects :-) Most non-mechanical electronic components will not suffer from immersion provided they are not powered up and provided that they dry out promptly so that they don't corrode. I would imagine this depends a lot on the water-tightness of individual package types (for example, tiny microSD cards look a lot more watertight than some bulky and cheap USB flash drives). MOXFYRE (contrib) 20:25, 5 June 2007 (UTC)

Data retention longevity?

I've been having some nasty disappointments with some CDs I used to store some data, which couldn't even survive a couple of years before being rendered unusuable. Motivated by that and by the price drop, I'm looking into the possibility of using flash cards to store my data. Unfortunately I can't find any information about the time I can expect the data to remain retrievable from flash memory. So, is it possible to add something about that in the article? --Mecanismo | Talk 09:37, 21 June 2007 (UTC)

See the Read-only_memory#Endurance_and_data_retention section of the ROM article (that section was written by me). It's pretty hard to put an exact number on flash, but several decades is probably about right in normal-temperature environments. With CD-Rs, there are a bunch of different processes and dyes that can be used, and some of them are just awful... as you've found out. I don't think there's as much variation with different types of flash, in part because it is a much more complicated thing to make, and there are fewer dodgy companies trying to make it. MOXFYRE (contrib) 12:21, 21 June 2007 (UTC)

Pictoral confusion

When I type in "flash memory" and this article loads, the first thing I saw was I picture of ram. I thought that I had gone to the wrong place and it took me a couple moments to notice that the picture of ram belonged to the volatile memory template. Perhaps, a picture of flash memory should lead the article ? —Preceding unsigned comment added by 138.87.231.215 (talk) 17:14, 10 October 2007 (UTC)

Nand Flash

Somebody may want to introduce this new information located here. I had a quick skim and couldn't find anything on this article about it. DoyleyTalk 11:43, 23 October 2007 (UTC)

Invention Year?

I'm suspicious about the claimed invention year of 1984 in the article. According to BusinessWeek the patent was filed in 1981, and according to an Economist article ("Not just a flash in the pan", 11 March 2006, which I got from the subscription-only NewsBank, I'm afraid) it was 1980... I can't find the patent to check; perhaps it was a Japanese patent? Does anyone know for sure, or have a citation for the patent? gothick (talk) 23:29, 14 February 2008 (UTC)

Here are some patents by Dr. Masuoka. US3825945 filed 1972 in Japan US4531203 filed 1980 in Japan

Dspark76 (talk) 18:55, 11 July 2008 (UTC)

first flash microcontroller

I've been told that the first flash microcontroller from each of 2 different companies was introduced in 1993:

• Atmel (8051 variant) in 1993[1]
• Microchip PIC16C84 in 1993[2].
• Atmel AVR claims "The AVR was one of the first microcontroller families to use on-chip flash memory for program storage" ... but, alas, doesn't give a year.

That may be the first from that particular company, but perhaps there is an earlier flash microcontroller from some other company?

Following on to the #Invention_Year.3F question:

• What year was the first flash memory chip was sold?
• What year was the first flash microcontroller was sold?

--68.0.124.33 (talk) 18:38, 22 February 2008 (UTC)

B-class rating

Hi y'all, since this article didn't have a rating, I decided to go ahead and rate it B-class. Reasons: I wouldn't/couldn't rate it GA-class without a group discussion and consensus, of course. Start-class would certainly be too low of a rating to give the article, since it's fairly sizeable with a decent coverage of the different aspects of the subject, so, at least for now, I think it fits well in the B-class zone of the rating system. --JamieS93 16:29, 3 March 2008 (UTC)

NAND memories corrections

• For error correcting code, the article only talk about hamming code. There should be a note about other algo need for correcting more than 1 bit (for MLC) : BLC or Reed–Solomon

• When a error is detected, the block isn't marked bad. It is only mark bad if there no way to erase it.

• The first physical block is not a bad block, but bit flip can happen. So it is not free from error and ecc should be used.

NOR flash chips lack intrinsic bad block management

The book "Nonvolatile Memory Technologies with Emphasis on Flash" by Brewer, J. and Gill, M, and published by Wiley Inter-Science states:

"NOR Flash guarantees 100% good bits, removing any need for error correcting code or controllers." page 22.

Who is right, the book or the wiki article? —Preceding unsigned comment added by Binarysaint (talk • contribs) 13:26, 30 April 2008 (UTC)

As a follow up, the following link also states "While NOR memories are error-free, NAND memories require bad-blocks to be detected and managed while writing to the device." - http://www.toyo.co.jp/sdp/dio/pdf/BBS.pdf Which also leads me to believe that the NOR section of this article incorrect. —Preceding unsigned comment added by Binarysaint (talk • contribs) 15:09, 30 April 2008 (UTC)

• The book. NOR Flash and NAND Flash are sold into entirely different marketplaces. If you're selling NOR, you are guaranteeing every single bit on the device is good. It's just how that market works, perhaps because NOR is frequently used for XIP and code storage where errors cannot be tolerated (or corrected). NAND is sold with bad bits and heavy on-chip error correction capability. The market tolerates this for NAND, probably because it's not much additional overhead (on top of the complex machinery required just to handle reads and writes) to address error checking and correction. Being able to sell every die manufactured makes the per-chip cost for NAND lower, which also makes the interface complexity more tolerable than NOR. Fhaigia (talk) 07:24, 16 August 2008 (UTC)

NOR flash wiring drawing

The drawing for NOR flash looks confusing with the explanation of the operation. Let's say the source is grounded and drain is HIGH. Now we have one word line HIGH and the adjacent one at 0V. It would appear the 0V floating gate would be erased (electrons pulled off to drain) while the HIGH word line would be written (electrons forced onto floating gate). So I would expect the drain cannot be shared between two gates.218.168.215.209 (talk) 12:41, 5 May 2008 (UTC)

• The drains of cells in a column all share a connection, called the bitline. The control gates of cells in a row all share a connection, called the wordline. To program a cell, both the CG and drain must be high, which only happens at one bitline/wordline junction at a time. Other cells that share a bitline with the cell being programmed will have a high drain but not a high CG. The low CG inhibits current flow, so the cells do not program. Other cells that share a wordline with the cell being programmed will have a high CG but not a high drain. The field from the CG creates a channel in the substrate, but there is no potential across the channel (source to drain) so no current flows and again, the cells do not program. Fhaigia (talk) 07:36, 16 August 2008 (UTC)

Spread of charge along floating gate

The floating gate is usually drawn under the control gate, as if parallel. It doesn't take much imagination to see that charge stored on the floating gate would spread out along the floating gate line, as far as possible, even beyond the cell boundary (e.g., to adjacent bit lines). Shouldn't there be any discussion as to how this can be limited?218.168.215.209 (talk) 21:18, 5 May 2008 (UTC)

The picture (Image:Flash_cell_structure.svg) is just showing a cross-section. The floating gate is limited in its extent perpendicular to the page. Does that make it clearer? ǝɹʎℲxoɯ (contrib) 21:35, 5 May 2008 (UTC)

Yes, thanks, that makes more sense.218.168.212.220 (talk) 10:18, 6 May 2008 (UTC)

NAND single transistor operation?

Is there any place where principles of NAND transistor (worht copying here) are described? Something like 'it conducts current if floating gate is charged to logical '1' AND regular gate is in logical '1', so they can be organised in stack, and read plane-after-plane by setting all bit lines except one to logical '1'. In companies' design guides there is nothing more than 'NOR flash functions like this-and-this, however our NAND flash is faster and cheaper' Linefeed (talk) 18:08, 9 June 2008 (UTC)

• NAND transistors (to a basic level of understanding) aren't any different than NOR transistors. They're all MOSFETs with an extra floating gate. The difference is in how the transistors are wired together. If the FG is holding a bunch of charge, the transistor's threshold voltage is higher and it will not pass (much) current during a read operation. This is read as a logical zero, i.e. "programmed." If the FG is free of charge, the threshold voltage is low and current will pass through the transistor during read. This is read as a logical one, i.e. "erased." In either programmed or erased state, if the CG voltage is made high enough (where "enough" means greater than the threshold voltage), a channel is created in the substrate and current may pass from drain to source. For simplicity, I've described SLC operation, but the concept is the same for MLC. Fhaigia (talk) 08:00, 16 August 2008 (UTC)

I agree with Fhaigia on the technical details. So I deleted the misleading statement that "NAND flash has a different internal structure", and edited to emphasize that both NAND flash and NOR flash use "floating-gate transistors".

What else can we do to make sure the readers of this article come to a correct understanding? Do the links to MOSFET and floating gate transistor properly support the rest of the "Flash memory" article? --68.0.124.33 (talk) 19:15, 11 August 2009 (UTC)

Charge-trapping vs. floating gate

The floating gate technology is likely to be succeeded by charge-trapping nitride (or other dielectric). This article could use an update on this new technology.218.168.205.182 (talk) 21:52, 21 June 2008 (UTC)

• Do you have a source? If so it can be added (perhaps even by you!) to the article without too much trouble. I ask because I don't have a source on that and I'm not sure exactly what you're talking about, so I'm not even sure where/what to look to find a source on nitride charge-trapping dialectrics. Fhaigia (talk) 08:03, 16 August 2008 (UTC)

I think 218.168.205.182 is talking about SONOS memory. I've used several flash microcontrollers; their documentation always refers to their integrated program memory as "flash memory" or occasionally "ROM memory" (sic). Recently I found out that one of them (the PSoC) actually uses SONOS memory rather than floating-gate flash memory. As far as I can tell, that microcontroller has been using SONOS since it was introduced in 2002.

I just added one sentence to this "Flash memory" article mentioning SONOS -- should we say anything else about it here?

My sources describe SONOS as a kind of Flash memory, so that's how I described it in this article.

I'm kind of hoping that someone will find some other source that has crisp definitions and 3 different names for "memory implemented by storing charge on floating gates made of conductive polysilicon" vs "memory implemented by storing charge in non-conductive nitride" vs. "non-volatile memory that is programmed and erased in large blocks, no matter how it is implemented."

Currently we have only 2 names ("SONOS" and "Flash"), and I've made things more ambiguous and confusing -- sorry! -- by using "Flash" to refer to 2 of those 3 things.

--68.0.124.33 (talk) 18:43, 11 August 2009 (UTC)

CFI vs. vendor specifc command sets for NOR Flash devices

The article states the following:

When unlocking, erasing or writing NOR memories, special commands are written to the first page of the mapped memory. These commands are defined by the Common Flash memory Interface (CFI) and the flash chips can provide a list of available commands to the physical driver.

This is both an incomplete and inaccurate description of NOR Flash programming. CFI is used to get information about the devices (geometry, command set, manufacturer, etc.) in an industry standard way, but is not used for programming (erase/write/unlock/lock, etc.) the device.

There are at least two different, and incompatible, command sets and "algorithms" used in current NOR Flash, and even within those two, there are variations. The two algorithms that I've had to work with are AMD/Fujitsu and Intel. Intel (along with STMicroelectronics and Francisco Partners) has recently spun off their non-volatile memory products into a new company, Numonyx, and AMD/Fujitsu have a joint venture, Spansion.

The article text needs to be updated, though I don't have the time to do it myself at the moment. --17:01, 8 July 2008 (UTC)205.175.225.28 (talk)

Question: what if block 0 goes bad?

The article says this:

The first physical block (block 0) is always guaranteed to be readable and free from errors.

What happens if block 0 goes bad after some usage? Is it possible to remap block 0? Or does that make a flash memory unusable? --Doradus (talk) 13:20, 16 July 2008 (UTC)

Apple

The point about Apple being the 3rd largest purchaser of flash memory is irrelevant. Also, why not say the #1 purchaser? --63.173.0.195 (talk) 15:13, 18 July 2008 (UTC)

Endurance inconsistency

In the History section, the article says NAND flash has 10x endurance over NOR. Later in the Endurance section, the article says the exact opposite (NOR is 10x endurance over NAND). Can someone straighten that out (and then remove this comment)? —Preceding unsigned comment added by 207.174.191.50 (talk) 06:22, 1 August 2008 (UTC)

By device operation the NAND device should have better endurance than NOR: They used only tunneling programming and not hot channel electron programming. However endurance and performance are strongly related and depending on the tradeoff taken by the industrial,it's hard to say what is the best at the component level. —Preceding unsigned comment added by 83.201.20.127 (talk) 14:39, 26 October 2008 (UTC)

On the subject of write endurance, much of it is duplicated in the "Limitations" section. Could some of the redundancy be reduced by the latter deferring some of the more technical points to the former? —Preceding unsigned comment added by 125.237.144.87 (talk) 19:28, 17 April 2010 (UTC)

Successive write capability

A location can [...] be rewritten as long as the new value's 0 bits are a superset of the over-written values. [...] In practice few algorithms can take advantage of this successive write capability [...].

I've added a 'citation needed' template here: is there any published research on this? Are there any examples of algoritms that do take advantage of this property? If not, where does this 'in practice' thing come from? --Tinctorius (talk) 22:30, 2 January 2009 (UTC)

I don't know of citations, but might want to look at some of the Flash file systems, and articles/sources about them. That would be one logical place to find software that exploits the characteristics of flash memory. (e.g. prefer certain bit transitions to indicate certain common flag changes). Zodon (talk) 22:53, 2 January 2009 (UTC)

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