Talk:Charge-pump phase-locked loop

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The pull-in range (capture range, acquisition range) of CP-PLL

F. Gardner, in the conclusion of his pioneering work^[1]^: 1856, conjectured that "transient response of practical charge-pump PLL's can be expected to be nearly the same as the response of the equivalent classical PLL."

By analogy with the Egan conjecture on the pull-in range of type 2 APLL, Amr M. Fahim noted about CP-PLL that ^[2]^: 6 "in order to have an infinite capture range, an active filter must be used for the loop filter".

B. Razavi noted regarding the CP-PLL that "We wish to develop a PLL that locks regardless of the initial value of the output frequency. Such a PLL would have an acquisition range equal to the VCO tuning range, with no limitations imposed by the loop bandwidth" and "The PFD concept eliminates the trade-off between the acquisition range and the loop bandwidth."^[3]^{: 224, 226}, and that "the combination of a PFD and a charge pump offers two important advantages ... 1) the capture range is only limited by the VCO output frequency range"^[4]^: 29.

In the book^[5]^: 32 it is noted that "The charge-pump PLL has two poles at the origin (type-II) in its open-loop transfer function. It locks faster and its static phase error is zero if mismatches and leakages are negligible. Moreover, its capture range is only limited by its VCO tuning range".

nk (talk) 05:54, 3 October 2020 (UTC)[reply]

References

^ F. Gardner (1980). "Charge-pump phase-lock loops". IEEE Transactions on communications. 28 (11): 1849–1858.
^ Fahim, Amr M. (2005). Clock Generators for SOC Processors: Circuits and Architecture. Boston-Dordrecht-London: Kluwer Academic Publishers.
^ Razavi, Behzad (2020). Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge: Cambridge University Press.
^ Razavi, Behzad (1996). Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. New York: John Wiley & Sons.
^ Keliu, Shu; Sanchez-Sinencio, Edgar (2005). CMOS PLL Synthesizers: Analysis and Design. New York: Springer Science & Business Media.

Gardner approximation

Gardner’s analysis is based on the following approximation: time interval on which PFD has non-zero state on each period of reference signal is

t_{p}=|\theta _{e}|/\omega _{\rm {ref}},\ \theta _{e}=\theta _{\rm {ref}}-\theta _{\rm {vco}}.

Then averaged output of charge-pump PFD is

i_{d}=I_{p}\theta _{e}/2\pi

with corresponding transfer function

I_{d}(s)=I_{p}\theta _{e}(s)/2\pi

Using filter transfer function $F(s)=R+{\frac {1}{Cs}}$ and VCO transfer function $\theta _{\rm {vco}}(s)=K_{\rm {vco}}I_{d}(s)F(s)/s$ one gets Gardner's linear approximated average model of second-order CP-PLL

{\frac {\theta _{e}(s)}{\theta _{\rm {ref}}(s)}}={\frac {2\pi s}{2\pi s+K_{\rm {vco}}I_{p}\left(R+{\frac {1}{Cs}}\right)}}

"In some sense, the loop operates on sampled basis and not as a straightforward continuous-time circuit. A sampled system almost always has more stability problems than arise in continuous-time systems. In particular, ananalog, second-order PLL is unconditionally stable for any value of loop gain, but the sampled equivalent will go unstable if the gain is made too large."^[1]

--Marat Yuldashev 12:21, 8 June 2020 (UTC)

Hold-in range of CP-PLL

Gardner's estimate^[1] of local stability (hold-in range):

\omega _{\rm {ref}}>{\frac {1}{4}}\left(K_{\rm {vco}}I_{p}R+{\sqrt {(K_{\rm {vco}}I_{p}R)^{2}+4{\frac {K_{\rm {vco}}I_{p}}{C}}}}\right)

plus VCO overload condition

\omega _{\rm {ref}}>K_{\rm {vco}}I_{p}R

According to Gardner "for any practical circuit" VCO overload condition dominates local stability one. — Preceding unsigned comment added by Maratyv (talk • contribs) 20:58, 4 June 2020 (UTC)[reply]

References

^ ^a ^b Cite error: The named reference Gardner-1980 was invoked but never defined (see the help page).

8-NOV-2024 Possible COI

The editor Kuznetsov N.V. appears to have added several sources published by them to this article. As such, I'm placing the COI maintenance template on the page to alert readers. Spintendo 11:52, 9 November 2024 (UTC)[reply]

[Gardner-1980-1] F. Gardner (1980). "Charge-pump phase-lock loops". IEEE Transactions on communications. 28 (11): 1849–1858.

[2005-Fahim-2] Fahim, Amr M. (2005). Clock Generators for SOC Processors: Circuits and Architecture. Boston-Dordrecht-London: Kluwer Academic Publishers.

[2020-Razavi-3] Razavi, Behzad (2020). Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge: Cambridge University Press.

[1996-Razavi-4] Razavi, Behzad (1996). Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. New York: John Wiley & Sons.

[2005-Shu-Sanchez-Sinencio-5] Keliu, Shu; Sanchez-Sinencio, Edgar (2005). CMOS PLL Synthesizers: Analysis and Design. New York: Springer Science & Business Media.

[Gardner-1980-6] Cite error: The named reference Gardner-1980 was invoked but never defined (see the help page).

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