Jump to content

Steamroller (microarchitecture)

From Wikipedia, the free encyclopedia
Steamroller - Family 15h (3rd-gen)
General information
LaunchedJanuary 14, 2014; 10 years ago (January 14, 2014)
Common manufacturer
Architecture and classification
Technology node28 nm SHP[1]
Instruction setAMD64 (x86-64)
Physical specifications
Sockets
Products, models, variants
Core name
History
PredecessorPiledriver - Family 15h (2nd-gen)
SuccessorExcavator - Family 15h (4th-gen)
Support status
iGPU unsupported

AMD Steamroller Family 15h is a microarchitecture developed by AMD for AMD APUs, which succeeded Piledriver in the beginning of 2014 as the third-generation Bulldozer-based microarchitecture.[2] Steamroller APUs continue to use two-core modules as their predecessors, while aiming at achieving greater levels of parallelism.

Microarchitecture

[edit]

Steamroller still features two-core modules found in Bulldozer and Piledriver designs called clustered multi-thread (CMT), meaning that one module is marketed as a dual-core processor.[3] The focus of Steamroller is for greater parallelism.[4] Improvements center on independent instruction decoders for each core within a module, 25% more of the maximum width dispatches per thread, better instruction schedulers, improved perceptron branch predictor, larger and smarter caches, up to 30% fewer instruction cache misses, branch misprediction rate reduced by 20%, dynamically resizable L2 cache, micro-operations queue,[5] more internal register resources and improved memory controller.

AMD estimated that these improvements will increase instructions per cycle (IPC) up to 30% compared to the first-generation Bulldozer core while maintaining Piledriver's high clock rates with decreased power consumption.[3] The final result was a 9% single-threaded IPC improvement, and 18% multi-threaded IPC improvement over Piledriver.[6]

Steamroller, the microarchitecture for CPUs, as well as Graphics Core Next, the microarchitecture for GPUs, are paired together in the APU lines to support features specified in Heterogeneous System Architecture.

History

[edit]

In 2011, AMD announced a third-generation Bulldozer-based line of processors for 2013,[7] with Next Generation Bulldozer as the working title, using the 28 nm manufacturing process.[8]

On 21 September 2011, leaked AMD slides indicated that this third generation of Bulldozer core was codenamed Steamroller.[9][10]

In January 2014, the first Kaveri APUs became available.[11]

Starting from May 2015 till March 2016 new APUs were launched as Kaveri-refresh (codenamed Godavari).[12]

Features

[edit]

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

[ VisualEditor ]
Platform High, standard and low power Low and ultra-low power
Codename Server Basic Toronto
Micro Kyoto
Desktop Performance Raphael Phoenix
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne
Entry
Basic Kabini Dalí
Mobile Performance Renoir Cezanne Rembrandt Dragon Range
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Lucienne 		Cezanne
Barceló 		Phoenix
Entry Dalí Mendocino
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge Pollock
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon 		Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family 		Prairie Falcon Banded Kestrel River Hawk
Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 2015 Jun 2015 Jun 2016 Oct 2017 Jan 2019 Mar 2020 Jan 2021 Jan 2022 Sep 2022 Jan 2023 Jan 2011 May 2013 Apr 2014 May 2015 Feb 2016 Apr 2019 Jul 2020 Jun 2022 Nov 2022
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[13] Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Bobcat Jaguar Puma Puma+[14] "Excavator+" Zen Zen+ "Zen 2+"
ISA x86-64 v1 x86-64 v2 x86-64 v3 x86-64 v4 x86-64 v1 x86-64 v2 x86-64 v3
Socket Desktop Performance — AM5 — —
Mainstream — AM4 — —
Entry FM1 FM2 FM2+ FM2+[a], AM4 AM4 —
Basic — — AM1 — FP5 —
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FP7 FL1 FP7
FP7r2
FP8 		? FT1 FT3 FT3b FP4 FP5 FT5 FP5 FT6
PCI Express version 2.0 3.0 4.0 5.0 4.0 2.0 3.0
CXL — —
Fab. (nm) GF 32SHP
(HKMG SOI) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N7
(FinFET bulk) 		TSMC N6
(FinFET bulk) 		CCD: TSMC N5
(FinFET bulk)
cIOD: TSMC N6
(FinFET bulk) 		TSMC 4nm
(FinFET bulk) 		TSMC N40
(bulk) 		TSMC N28
(HKMG bulk) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N6
(FinFET bulk)
Die area (mm2) 228 246 245 245 250 210[15] 156 180 210 CCD: (2x) 70
cIOD: 122 		178 75 (+ 28 FCH) 107 ? 125 149 ~100
Min TDP (W) 35 17 12 10 15 65 35 4.5 4 3.95 10 6 12 8
Max APU TDP (W) 100 95 65 45 170 54 18 25 6 54 15
Max stock APU base clock (GHz) 3 3.8 4.1 4.1 3.7 3.8 3.6 3.7 3.8 4.0 3.3 4.7 4.3 1.75 2.2 2 2.2 3.2 2.6 1.2 3.35 2.8
Max APUs per node[b] 1 1
Max core dies per CPU 1 2 1 1
Max CCX per core die 1 2 1 1
Max cores per CCX 4 8 2 4 2 4
Max CPU[c] cores per APU 4 8 16 8 2 4 2 4
Max threads per CPU core 1 2 1 2
Integer pipeline structure 3+3 2+2 4+2 4+2+1 1+3+3+1+2 1+1+1+1 2+2 4+2 4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF Yes Yes
IOMMU[d] — v2 v1 v2
BMI1, AES-NI, CLMUL, and F16C Yes — Yes
MOVBE — Yes
AVIC, BMI2, RDRAND, and MWAITX/MONITORX — Yes
SME[e], TSME[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing — Yes — Yes
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT — Yes — Yes
MPK, VAES — Yes —
SGX — —
FPUs per core 1 0.5 1 1 0.5 1
Pipes per FPU 2 2
FPU pipe width 128-bit 256-bit 80-bit 128-bit 256-bit
CPU instruction set SIMD level SSE4a[f] AVX AVX2 AVX-512 SSSE3 AVX AVX2
3DNow! 3DNow!+ — —
PREFETCH/PREFETCHW Yes Yes
GFNI — Yes —
AMX —
FMA4, LWP, TBM, and XOP — Yes — — Yes —
FMA3 Yes Yes
AMD XDNA — Yes —
L1 data cache per core (KiB) 64 16 32 32
L1 data cache associativity (ways) 2 4 8 8
L1 instruction caches per core 1 0.5 1 1 0.5 1
Max APU total L1 instruction cache (KiB) 256 128 192 256 512 256 64 128 96 128
L1 instruction cache associativity (ways) 2 3 4 8 2 3 4 8
L2 caches per core 1 0.5 1 1 0.5 1
Max APU total L2 cache (MiB) 4 2 4 16 1 2 1 2
L2 cache associativity (ways) 16 8 16 8
Max on--die L3 cache per CCX (MiB) — 4 16 32 — 4
Max 3D V-Cache per CCD (MiB) — 64 — —
Max total in-CCD L3 cache per APU (MiB) 4 8 16 64 4
Max. total 3D V-Cache per APU (MiB) — 64 — —
Max. board L3 cache per APU (MiB) — —
Max total L3 cache per APU (MiB) 4 8 16 128 4
APU L3 cache associativity (ways) 16 16
L3 cache scheme Victim Victim
Max. L4 cache — —
Max stock DRAM support DDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR5-4800, LPDDR5-6400 DDR5-5200 DDR5-5600, LPDDR5x-7500 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400 DDR4-1600 DDR4-3200 LPDDR5-5500
Max DRAM channels per APU 2 1 2 1 2
Max stock DRAM bandwidth (GB/s) per APU 29.866 34.132 38.400 46.932 68.256 102.400 83.200 120.000 10.666 12.800 14.933 19.200 38.400 12.800 51.200 88.000
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen[16] RDNA 2 RDNA 3 TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen[16] GCN 5th gen RDNA 2
GPU instruction set TeraScale instruction set GCN instruction set RDNA instruction set TeraScale instruction set GCN instruction set RDNA instruction set
Max stock GPU base clock (MHz) 600 800 844 866 1108 1250 1400 2100 2400 400 538 600 ? 847 900 1200 600 1300 1900
Max stock GPU base GFLOPS[g] 480 614.4 648.1 886.7 1134.5 1760 1971.2 2150.4 3686.4 102.4 86 ? ? ? 345.6 460.8 230.4 1331.2 486.4
3D engine[h] Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 Up to 704:44:16[17] Up to 512:32:8 768:48:8 128:8:4 80:8:4 128:8:4 Up to 192:12:8 Up to 192:12:4 192:12:4 Up to 512:?:? 128:?:?
IOMMUv1 IOMMUv2 IOMMUv1 ? IOMMUv2
Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0[18] VCN 2.1[19] VCN 2.2[19] VCN 3.1 ? UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.2 VCN 1.0 VCN 3.1
Video encoder — VCE 1.0 VCE 2.0 VCE 3.1 — VCE 2.0 VCE 3.4
AMD Fluid Motion No Yes No No Yes No
GPU power saving PowerPlay PowerTune PowerPlay PowerTune[20]
TrueAudio — Yes[21] ? — Yes
FreeSync 1
2 		1
2
HDCP[i] ? 1.4 2.2 2.3 ? 1.4 2.2 2.3
PlayReady[i] — 3.0 not yet — 3.0 not yet
Supported displays[j] 2–3 2–4 3 3 (desktop)
4 (mobile, embedded)		 4 2 3 4 4
/drm/radeon[k][23][24] Yes — Yes —
/drm/amdgpu[k][25] — Yes[26] — Yes[26]
  1. ^ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. ^ A PC would be one node.
  3. ^ An APU combines a CPU and a GPU. Both have cores.
  4. ^ Requires firmware support.
  5. ^ a b Requires firmware support.
  6. ^ No SSE4. No SSSE3.
  7. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. ^ Unified shaders : texture mapping units : render output units
  9. ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. ^ To feed more than two displays, the additional panels must have native DisplayPort support.[22] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

Processors

[edit]

APU lines

[edit]
Main articles: "Kaveri" desktop processors and "Kaveri" mobile processors
  1. Kaveri A-series APU
  2. Berlin APU - canceled
    • Announced in 2013 by AMD[36] the Berlin APU were targeted at the enterprise and server markets featuring four Steamroller cores, up to 512 stream processors and support for ECC memory.

FX lines (discontinued)

[edit]
Main article: List of AMD FX microprocessors

In November 2013 AMD confirmed it would not update the FX series in 2014, neither its Socket AM3+ version, nor will it receive a Steamroller version with a new socket.[37][38]

AMD however, released a Kaveri based FX-770K for desktop and FX-7600P for mobile which are basically APUs with their integrated graphics disabled similar to the Athlon X4 FM2+ line. Those APUs were released for OEMs only.

Server lines (canceled)

[edit]
Main article: List of AMD Opteron microprocessors

AMD's server roadmaps for 2014 showed:[39][40]

  • Berlin APU - quad-core x86 Steamroller architecture (as described above) for 1 Processor (1P) compute and media clusters
  • Berlin CPU - quad-core x86 Steamroller architecture for 1P web and enterprise services clusters
  • Seattle CPU - 4/8 core AArch64 Cortex-A57 architecture (Opteron A1100) for 1P web and enterprise services clusters [41]
  • Warsaw CPU - up to 16 core x86 Piledriver (2nd gen Bulldozer) architecture (Opteron 6338P and 6370P) for 2P/4P servers [42]

However, plans for Steamroller Opteron products were cancelled, likely due to the poor energy efficiency achieved in this generation of the Bulldozer architecture. Energy efficiency was greatly increased in the following generation, Excavator, which exceeded Jaguar in performance per watt, and approximately doubled performance/watt over Steamroller (for example 20.74 pt/W vs 10.85 pt/W when comparing similar mobile APUs using rough arbitrary metrics).[43][44]

References

[edit]
  1. ^ "Page 2 - AMD Kaveri A10-7850K and A8-7600 review: Was it worth the wait for the first true heterogeneous chip?". ExtremeTech. Retrieved 2014-02-19.
  2. ^ "AMD Kaveri Review: A8-7600 and A10-7850K Tested". Anandtech.com. 2014-01-14. Retrieved 2014-02-08.
  3. ^ a b "AMD: We Are On Track With Steamroller Micro-Architecture in 2013". X-bit labs. 2013-03-31. Archived from the original on 2013-10-25. Retrieved 2013-09-29.
  4. ^ Su, Lisa (2012-02-02). "Consumerization, Cloud, Convergence" (PDF). AMD 2012 Financial Analyst Day. Sunnyvale, California: Advanced Micro Devices. p. 26. Retrieved 2012-02-04.
  5. ^ Anand Lal Shimpi (2012-08-28). "AMD's Steamroller Detailed: 3rd Generation Bulldozer Core". Retrieved 2013-11-16.
  6. ^ Miller, Michael J. (2014-02-14). "Ivytown, Steamroller, 14 and 16nm Process Highlight ISSCC". Forwardthinking.pcmag.com. Retrieved 2014-02-19.
  7. ^ Anton Shilov (2010-11-09). "AMD Plans to Release Twenty-Core Microprocessor in 2012". X-bit labs. Archived from the original on 2012-02-05. Retrieved 2012-01-23.
  8. ^ "2012 Financial Analyst Day". 2012-02-02. Archived from the original on 2014-09-06. Retrieved 2013-09-29.
  9. ^ "Hosszútávú mobil útiterv szivárgott ki az AMD-től - PROHARDVER! Processzor hír". Prohardver.hu. 2011-09-21. Retrieved 2012-01-23.
  10. ^ "Nuove roadmap AMD sulle future APU in programma nel 2012 e nel 2013 per il mercato mobile". 2011-09-21. Archived from the original on 2013-01-11. Retrieved 2012-01-23.
  11. ^ Joel Hruska (2014-01-14). "AMD Kaveri A10-7850K and A8-7600 review: Was it worth the wait for the first true heterogeneous chip?". extremetech.com. Retrieved 2014-01-17.
  12. ^ "12 款 APU 及 CPU 準備出發，「Godavari」為 AMD 產品新代號". VR-Zone. Archived from the original on 11 February 2017. Retrieved 8 February 2017.
  13. ^ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  14. ^ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  15. ^ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  16. ^ a b "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  17. ^ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  18. ^ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  19. ^ a b "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021.
  20. ^ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  21. ^ "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  22. ^ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  23. ^ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
  24. ^ "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
  25. ^ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  26. ^ a b Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
  27. ^ "AMD Unleashes More Details About Kaveri: HSA, TrueAudio, Mantle". Archived from the original on 2016-08-04. Retrieved 2013-11-16.
  28. ^ "AMD's Next-Gen "Kaveri" APUs Will Require New Mainboards". 30 May 2013. Archived from the original on 7 June 2013. Retrieved 9 June 2013.
  29. ^ "A technical look at AMD's Kaveri architecture". SemiAccurate. 15 January 2014.
  30. ^ "AMD Kaveri APU Architecture Detailed". 4 July 2013.
  31. ^ "Multi-monitor: Civilization V on A10-7850K "Kaveri"". YouTube.
  32. ^ "AMD A8-7600 Kaveri APU review - The Embedded GPU - HSA & hUMA". 14 January 2014.
  33. ^ "AMD A10-7850K Graphics Performance". 14 February 2014. Retrieved 2 April 2014.
  34. ^ "AMD to add ARM processors to boost chip security". 14 June 2012. Retrieved 3 September 2013.
  35. ^ "AMD and ARM Fusion redefine beyond x86". Retrieved 10 November 2013.
  36. ^ "AMD Berlin Server APU Provides Glimpse At Upcoming Kaveri APU With 4 Steamroller Cores and 512 GCN SPs". 19 June 2013. Retrieved 29 September 2013.
  37. ^ Anton Shilov (2013-11-13). "AMD Cans Plans to Introduce Next-Gen FX Microprocessors Next Year". xbitlabs.com. Archived from the original on 2019-12-01. Retrieved 2013-11-16.
  38. ^ Josh Walrath (2013-09-04). "AMD's Processor Shift: The Future Really is Fusion". Retrieved 2013-09-29.
  39. ^ "Berlin, Warsaw are the future of AMD's x86 server lineup". The Tech Report. 2013-06-18. Retrieved 2013-09-29.
  40. ^ Mujtaba, Hassan (December 26, 2013). "AMD Opteron Roadmap Reveals Next Generation Toronto and Carrizo APU Details". WCCF Tech. Retrieved January 15, 2015.
  41. ^ Mendoza, Menchie (August 13, 2014). "AMD unwraps 64-bit ARM 'Seattle' server chip". Tech Times. Retrieved January 15, 2015.
  42. ^ Gasior, Geoff (January 22, 2014). "16-core Warsaw CPUs added to Opteron lineup". The Tech Report. Retrieved January 15, 2015.
  43. ^ "Opteron X2150 vs A10 8700P". cpuboss.com. Archived from the original on November 16, 2016. Retrieved November 15, 2016.
  44. ^ "AMD A10 8700P vs 7300". cpuboss.com. Archived from the original on November 27, 2016. Retrieved November 15, 2016.
Retrieved from "https://en.wikipedia.org/w/index.php?title=Steamroller_(microarchitecture)&oldid=1244407786"