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August 1

What's the most powerful fully open source CPU design showing where every transistor goes?

Referring to the physical design in the silicon. Not that most, if any, individual people even have Czochralski pullers, fab equipment, etc... 20.137.2.50 (talk) 15:50, 1 August 2013 (UTC)[reply]

Maybe OpenCores? 2A02:8422:1191:6E00:56E6:FCFF:FEDB:2BBA (talk) 17:41, 1 August 2013 (UTC)[reply]

I'm not sure you'll find one all the way down to the transistors. Most open-source CPUs seem to be implemented in FPGAs, so they're only implemented to the VHDL level. You could investigate how one compiles to a specific FPGA, but that isn't really the same as a silicon design that could be fabbed. 209.131.76.183 (talk) 19:31, 1 August 2013 (UTC)[reply]

So want the shemas used to burn the chip? I know for Ares on PCB. Which software could be used for IC? 2A02:8422:1191:6E00:56E6:FCFF:FEDB:2BBA (talk) 20:43, 1 August 2013 (UTC)[reply]

Interesting, IC layouts have their own class of intellectual property protection. 75.75.42.89 (talk) 23:23, 1 August 2013 (UTC)[reply]

OpenRISC has several variants. OpenSPARC has several variants. Both are available on OpenCores.org. To evaluate these comparatively, you'll have to specify what you mean by "most powerful." You'll also need to account for how much the performance scales with process, and how much the process is limited by your EDL software. I am not aware of any open-source toolkit that can synthesize OpenRISC or OpenSPARC; a GNU VHDL toolkit exists, but I have never seen it work in practice on anything nontrivial. Some years ago, as a researcher, I compiled OpenRISC 1000 using commercial tools (Design Compiler from Synopsys); so even though the CPU architecture and code were opensource and free software, my resulting RTL was not. Then I synthesized the RTL using Altera's design suite for Cyclone. So the synthesis and timing analysis were also non-free. I simulated my design in silicon using a TSMC process, so my silicon realization was also based on commercial non-free tools and process.

I do not believe that any totally-free toolchain is capable of the full conversion from a high-level CPU architecture description (e.g. in VHDL) to a gate-level format suitable for layout and fabrication - or even realization in a programmable gate array device (FPGA or PLA). This area of engineering - electronic design automation - is characteristically done using very proprietary methods and very expensive, clunky, commercial software. And I'm seeing a lot more red-links, indicating that as of my posting, we don't even have articles on them... Nimur (talk) 03:45, 2 August 2013 (UTC)[reply]

Interesting, prior to reading the TSMC article, I didn't know that AMD was fabless. 20.137.2.50 (talk) 13:52, 2 August 2013 (UTC)[reply]

I think it says AMC, not AMD... --Tardis (talk) 04:27, 4 August 2013 (UTC)[reply]

As of this writing, AMD (Advanced Micro Devices, the major CPU vendor, who competes with Intel in consumer-computer and server markets) is fabless. AMD's semiconductor manufacturing division was sold as a separate company, GlobalFoundries, a few years ago. Nimur (talk) 22:04, 4 August 2013 (UTC)[reply]