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2--VHDL
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VHDL (VHSIC hardware description language) is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits. Contents [hide]
* 1 History
* 2 Discussion
* 3 Getting started
* 4 Code examples
o 4.1 Synthesizeable constructs and VHDL templates
o 4.2 MUX templates
o 4.3 Latch templates
o 4.4 D-type flip-flops
o 4.5 The counter example
o 4.6 Fibonacci series
o 4.7 Simulation-only constructs
* 5 References
* 6 See also
* 7 External links
* 8 Further reading
[edit] History
VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.
The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest cost, highest power efficiency, highest speed, or other requirements.
VHDL borrows heavily from the Ada (programming language) in both concepts (for example, the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly-typed and case insensitive. There are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor, in order to represent directly operations which are common in hardware. VHDL also allows arrays to be indexed in either direction (ascending or descending) because both conventions are used in hardware, whereas Ada (like most programming languages) provides ascending indexing only. The reason for the similarity between the two languages is that the Department of Defense required as much as possible of the syntax to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada.
The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.
A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector.
The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.
Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.
In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.
Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions.
In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.
[edit] Discussion
VHDL is a fairly general-purpose language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog language. VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a holy war amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than D-type flip-flops as storage elements.
The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). This is unlike many of the other computing languages such as BASIC, Pascal, C, or lower-level assembly language which runs at machine code level, which all run sequentially, one instruction at a time on von Neumann architectures.
A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.
[edit] Getting started
As with any hardware or software language, becoming proficient in VHDL requires a commitment to study and practice. Although background in a computer programming language (such as C) is helpful, it is not essential. Today, free VHDL simulators are readily available, and although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user's goal is to learn RTL coding, i.e. design hardware circuits in VHDL (as opposed to simply document or simulate circuit behavior), then a synthesis/design package is also essential to the learning process.
As with VHDL simulators, free FPGA synthesis tools are readily available, and are more than adequate for independent study. Feedback from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design input methods, such as block-diagram (schematic) and state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures, or complex state-transition diagrams. Finally, the included tutorials and examples are valuable aids.
Nearly all FPGA design and simulation flows support both Verilog and VHDL, allowing the user to learn either or both languages. Here is a list of free design & simulation packages for VHDL/Verilog:
ISE Simulator Vendor Trial Software License Simulator Synthesizer RTL view Gate view Actel Libero gold one year free license ModelSim Actel Edition Synplify Actel Edition No *yes Aldec Active-HDL (Student Edition) one year free license Aldec (mixed language) Student All Synthesis (interfaces) yes yes Altera Quartus II web edition 6 months renewable free license ModelSim Altera Edition Altera Quartus II yes *yes Lattice ispLever starter 6 months renewable free license Precision/Synplify Lattice Edition No yes Mentor none free license ModelSim PE Student Edition no yes no Xilinx ISE webpack free license Xilinx XST yes *yes Blue Pacific BlueHDL free license BlueSim ? ? ?
- Limited to vendor's device-database
+ If Modelsim is installed on the computer, the ISE software can call ModelSim's features if desired.
[edit] Code examples
In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations.
A simple AND gate in VHDL would look something like this:
-- (this is a VHDL comment)
-- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all;
-- this is the entity entity ANDGATE is
port (
IN1 : in std_logic;
IN2 : in std_logic;
OUT1: out std_logic);
end ANDGATE; architecture RTL of ANDGATE is
begin
OUT1 <= IN1 and IN2;
end RTL;
While the example above may seem very verbose to HDL beginners, one should keep in mind that many parts are either optional or need to be written only once. In addition, use of elements such as the 'std_logic' type might at first seem an overkill. One could easily use the built-in 'bit' type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.
In the examples that follow, you will see that VHDL code can be written in a very compact form. However, the experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability. Another advantage to the verbose coding style is the smaller amount of resources used when programming to a Programmable Logic Device such as a CPLD.
[edit] Synthesizeable constructs and VHDL templates
Originally synthesizers, which would correspond to compilers in the HDL world, used a set of templates to identify the common hardware constructs in the HDL code (recall that VHDL is a hardware 'description' language, not a programming language). These templates can still be used today, although the HDL tools are far more sophisticated these days. Due to their usually one-to-one mapping to well known digital circuits, the templates are usually what an otherwise experienced hardware designer would use when entering the HDL world. But they are also useful for those who are completely new to digital design.
Some digital components have multiple templates, consider for instance the multiplexer example that follows:
[edit] MUX templates
The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs A and B, selector S and output X:
-- template 1: X <= A when S = '1' else B;
-- template 2: with S select X <= A when '1' else B;
-- template 3: process(A,B,S) begin
case S is when '1' => X <= A; when others => X <= B; end case;
end process;
-- template 4: process(A,B,S) begin
if S = '1' then X <= A; else X <= B; end if;
end process;
The two last templates make use of what VHDL calls 'sequential' code. The sequential sections are always placed inside a process and have a slightly different syntax which may resemble more traditional programming languages.
[edit] Latch templates
A transparent latch is basically one bit of memory which is updated when an enable signal is raised:
-- latch template 1: Q <= D when Enable = '1' else Q;
-- latch template 2: process(D,Enable) begin
if Enable = '1' then Q <= D; end if;
end process;
A SR-latch uses a set and reset signal instead:
-- SR-latch template 1: Q <= '1' when S = '1' else
'0' when R = '1' else Q;
-- SR-latch template 2: process(S,R) begin
if S = '1' then Q <= '1'; elsif R = '1' then Q <= '0'; end if;
end process;
Template 2 has an implicit "else Q <= Q;" which may be explicitly added if desired.
-- This one is a RS-latch (i.e. reset dominates) process(S,R) begin
if R = '1' then Q <= '0'; elsif S = '1' then Q <= '1'; end if;
end process;
[edit] D-type flip-flops
The D-type flip-flop samples an incoming signal at the rising or falling edge of a clock. The DFF is the basis for all synchronous logic.
-- simplest DFF template (not recommended) Q <= D when rising_edge(CLK);
-- recommended DFF template: process(CLK) begin
-- use falling_edge(CLK) to sample at the falling edge instead if rising_edge(CLK) then Q <= D; end if;
end process;
-- alternative DFF template: process begin
wait until rising_edge(CLK); Q <= D;
end process;
Some flip-flops also have Enable signals and asynchronous or synchronous Set and Reset signals:
-- template for asynchronous reset with clock enable: process(CLK, RESET) begin
if RESET = '1' then -- or '0' if RESET is active low...
Q <= '0';
elsif rising_edge(CLK) then
if Enable = '1' then -- or '0' if Enable is active low...
Q <= D;
end if;
end if;
end process;
-- template for synchronous reset with clock enable: process(CLK) begin
if rising_edge(CLK) then
if RESET = '1' then
Q <= '0';
elsif Enable = '1' then -- or '0' if Enable is active low...
Q <= D;
end if;
end if;
end process;
A common beginner mistake is to have a set or reset input but not use it. For example, the following two snippets are not equal, the first one is a simple D-type flip-flop, while the second one is a DFF with a feedback MUX.
-- simple D-type flip-flop process(CLK) begin
if rising_edge(CLK) then Q <= D; end if;
end process;
-- BAD VHDL: this does NOT make the flip-flop a DFF without a reset!! process(CLK, RESET) begin
if RESET = '1' then
-- do nothing. Q is not set here...
elsif rising_edge(CLK) then
Q <= D;
end if;
end process;
This is very similar to the 'transparent latch' mistake mentioned earlier.
[edit] The counter example
The following example is a counter with asynchronous reset, parallel load and configurable width. It demonstrates the use of the 'unsigned' type and VHDL generics. The generic are very close to templates in, for example, C++ or other traditional programming languages.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- for the unsigned type
entity counter_example is generic ( WIDTH : integer := 32); port (
CLK, RESET, LOAD : in std_logic; DATA : in unsigned(WIDTH-1 downto 0); Q : out unsigned(WIDTH-1 downto 0));
end entity counter_example;
architecture counter_example_a of counter_example is signal cnt : unsigned(WIDTH-1 downto 0); begin
Q <= cnt;
process(RESET, CLK)
begin
if RESET = '1' then
cnt <= (others => '0');
elsif rising_edge(CLK) then
if LOAD = '1' then
cnt <= DATA;
else
cnt <= cnt + 1;
end if;
end if;
end process;
end architecture counter_example_a;
[edit] Fibonacci series
The following example is slightly more complex:
-- Fib.vhd -- -- Fibonacci number sequence generator
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
entity Fibonacci is port (
Reset : in std_logic; Clock : in std_logic; Number : out unsigned(31 downto 0)
); end entity Fibonacci;
architecture Rcingham of Fibonacci is
signal Previous : natural; signal Current : natural; signal Next_Fib : natural;
begin
Adder:
Next_Fib <= Current + Previous;
Registers:
process (Clock, Reset) is
begin
if Reset = '1' then
Previous <= 1;
Current <= 1;
elsif rising_edge(Clock) then
Previous <= Current;
Current <= Next_Fib;
end if;
end process Registers;
Number <= to_unsigned(Previous, 32);
end architecture Rcingham;
When simulated, it generates the Fibonacci sequence successfully, until Next_Fib overflows the range of the natural type. When synthesized with an FPGA vendor's tools, an "Adder" module was implemented, as hoped for. Otherwise, the assignment statement would have to be replaced by a component instantiation to logic that implements that function.
[edit] Simulation-only constructs
A large subset of VHDL cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and can only be used for prototyping, simulation and debugging. For example, the following code will generate a clock with the frequency of 50 MHz. It can, for example, be used to drive a clock input in a design during simulation. It is however a simulation-only construct and can not be implemented in hardware!
process begin
CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns;
end process;
The simulation-only constructs can be used to build complex waveforms in very short time. Such waveform can be used, for example, as test vectors for a complex design or as a prototype of some synthesizable logic that will be implemented in future.
process begin
wait until START = '1'; -- wait until START is high for i in 1 to 10 loop -- then wait for a few clock periods... wait until rising_edge(CLK); end loop; for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA <= to_unsigned(i, 8); wait until rising_edge(CLK); end loop; -- wait until the output changes wait until RESULT'event; -- now raise ACK for clock period ACK <= '1'; wait until rising_edge(CLK); ACK <= '0'; -- and so on...
end process;
[edit] References This article does not cite any references or sources. (August 2006) Please help improve this article by adding citations to reliable sources. Unverifiable material may be challenged and removed.
[edit] See also
* Verilog * SystemC * Register transfer level * Electronic design automation * Complex programmable logic device (CPLD)
[edit] External links Wikibooks Wikibooks Programmable Logic has a page on the topic of VHDL Module Structure
* The FAQ of news://comp.lang.vhdl * Designers Guide to VHDL * IEEE VASG (VHDL Analysis and Standardization Group) - Official VHDL Working Group * A VHDL reference design - UART (Testbench for the design) * GHDL, a complete Free Software VHDL compiler/simulator, built on top of GCC. * John's FPGA Page - List of VHDL and FPGA resources, including VHDL tutorials. * www.opencores.org - A home of many open source VHDL and Verilog projects
[edit] Further reading
* Johan Sandstrom. "Comparing Verilog to VHDL Syntactically and Semantically", Integrated System Design, EE Times, October 1995. — Sandstrom presents a table relating VHDL constructs to Verilog constructs. * Qualis Design Corporation (2000-07-20). "VHDL quick reference card". 1.1. Qualis Design Corporation. * Qualis Design Corporation (2000-07-20). "1164 packages quick reference card". 1.0. Qualis Design Corporation. * Qualis Design Corporation (2007-03-29). "VHDL quick reference card". 2.2. Qualis Design Corporation. * Qualis Design Corporation (2007-03-29). "1164 packages quick reference card". 2.2. Qualis Design Corporation.