User:Steven Hepting/Process variation (semiconductor)

Process variation is the naturally occuring difference in lengths and widths of transistors when integrated circuits are fabricated. It becomes particularly important at smaller process nodes (<65nm) as the variation becomes a larger percentage of the full length or width of the device and as feature sizes approach the fundamental dimensions such as the size of atoms and the wavelength of usable light for patterning lithography masks.

It causes problems with predicting the output performance of analog circuits due in particular to the mismatch it can cause.

History

The first mention of variation in semiconductors was by William Shockley in his 1961 analysis of junction breakdown. The ideas were later applied to MOS devices and variability in interconnects.

Workarounds & Solutions

Statistical Analysis

Designers using this approach run from tens to thousands of simulations to analyze how the outputs of the circuit will behave according to the measured variability of the transistors for that particular process. The measured criteria for transistors are recorded in model files given to designers for simulating their circuits before simulation.

The most basic approach is for designers to increase the size of devices which are sensitive to mismatch.

Topology Optimization

To reduce variation due to polishing etc

Patterning Techniques

To reduce roughness of line edges.

See Also

• Semiconductor fabrication
• Transistor models

External links

• CMOS process variations: are they inevitable, or a symptom or immaturity?
• Process Variations: A Critical Operation Point Hypothesis

Category:Semiconductor_device_fabrication