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[edit]Model | Release date | Family/ Product branding1 |
Fab Process |
Bus interface | Core | Memory | API support (version) |
Shader FLOPS performance |
Dual-GPU products |
Notes5 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Frequency | Config2 | Amount | Frequency (DDR/QDR equiv.)3 |
Bandwidth | Bus type | Bus width | DirectX | OpenGL | OpenCL | SP | DP | ||||||||
tick | R600 | May 2007 | Radeon HD 2900 series | 65 nm | PCIe x16 | 743 MHz | 320(64x5):16:16 | 512 - 1024 MiB | 825 MHz (1650) 1000 MHz (2000) |
105.6 GB/s 128.0 GB/s |
GDDR3 GDDR4 |
512-bit | 10 | 2.0/2.1 3.0/3.1 |
— | 475 GFLOPS | — | ||
tock | RV670 | November 2007 | Radeon HD 3800 series | 55 nm | PCIe 2.0 x16 | 775 MHz | 320(64x5):16:16 | 512 - 1024 MiB | 900 MHz (1800) 1125 MHz (2250) |
57.6 GB/s 72.0 GB/s |
GDDR3 GDDR4 |
256-bit | 10.1 | 2.0/2.1 3.0/3.1 |
1.0 | 496 GFLOPS | 99.2 GFLOPS | (R680) | |
tick | RV770 RV790 |
June 2008 April 2009 |
Radeon HD 4800 series Radeon HD 4890 |
55 nm | PCIe 2.0 x16 | 750 MHz 850 MHz |
800(160x5):40:16 | 512 - 1024 MiB 1024 MiB |
900 MHz (3600) 975 MHz (3900) |
115.2 GB/s 124.8 GB/s |
GDDR5 | 256-bit | 10.1 | 2.0/2.1 3.0/3.1 |
1.0 | 1200 GFLOPS | 240 GFLOPS | (R700) |
|
tock | RV740 | May 2009 | Radeon HD 4770 | 40 nm | PCIe 2.0 x16 | 750 MHz | 640(128x5):32:16 | 512 MiB | 800 MHz | 51.2 GB/s | DDR3/GDDR3 GDDR5 |
256-bit | 10.1 | 2.0/2.1 3.0/3.1 |
1.0 | 960 GFLOPS | 192 GFLOPS | ||
tick | RV870 | Q3 2009 | ? | 40 nm | PCIe 2.0 x16 | GDDR5 | 256-bit | 11 | 2.0/2.1 3.0/3.1 |
1.0 | (R800) | ||||||||
2010 | ? | PCIe 2.0 x16 | GDDR5 | 11 | |||||||||||||||
Notes: 1. Names in bracket () indicate temporary name 2. Core config notation: Unified Shaders (Vertex shader/Geometry shader/Pixel shader) : Texture mapping unit : Render Output unit 3. The effective data transfer rate of GDDR5 is quadruple its nominal clock, instead of double as with other DDR memory. 4. The theoretical shader performance in single-precision and double-precision (excluding Radeon HD 2000 series) floating point operations [FLOPSsp and FLOPSdp, GFLOPS] can be estimated by the following: (where shader count is n and core frequency is f measured in GHz) 5. Denotes future products, not all specifications are available |