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MIL-STD-1750A or 1750A is the formal definition of a 16-bit computer Instruction Set Architecture (ISA), including both required and optional components, as described by the military standard document MIL-STD-1750A (1980). In addition to the core ISA, the definition defines optional instructions, such as a FPU & MMU. Importantly, the standard does not define the implementation details of a 1750A processor.

Because MIL-STD-1750A did not define implementation details, 1750A products are available from a wide variety of companies in the form of component, board, and system-level offerings implemented in a myriad of technologies, often the most advanced and exotic of their respective periods (e.g. GaAs, ECL, SoS). Of particular interest is the fact that 1750A systems often offer very high levels of radiation and other hazardous environment protection, making them particularly suited for military, aviation and space applications.

The U.S. Air Force defined the standard in order to have a common computing architecture and thereby reduce the costs of software and computer systems for all military computing needs. This includes embedded tasks such as aircraft and missile control systems as well as more mundane general military computing needs. The advantages of this concept were recognized outside of the USAF and the 1750A was adopted by numerous other organizations, such as the European Space Agency, NASA, Israeli Aircraft Industries and many projects in academia. Examples of military aircraft using the 1750A include:

  • USAF F-18 RFCS Flight Control Computer
  • USAF F-16 Digital Flight Control System and Fire Control Computer
  • US Army AH-64D Apache Longbow Helicopter
  • IAI Lavi fighter
  • IBM Federal Systems AP-102 Avionics Computer (used in various roles including the USAF F-111 avionics upgrade)

Fully space rated implementations make the 1750A one of the few types of computers that are applicable for use in deep space applications. Example spacecraft that use the 1750A are:

Processors based on MIL-STD-1750A are usually programmed in JOVIAL, a high-level programming language defined by the United States Department of Defense which was derived from ALGOL 58. Older versions of GNU GCC contain support for MIL-STD-1750A; it was declared obsolete in version 3.1, and removed in subsequent versions.

The 1750A supports 216 16-bit words of memory for the core standard. The standard defines an optional memory management unit that allows 220 16-bit words of memory using 512 page mapping registers (in the I/O space), defining separate instruction and data spaces, and keyed memory access control.

Most instructions are 16 bits, although some have a 16-bit extension. The standard computer has 16 general purpose 16-bit registers (0 through 15). Registers 1 through 15 can be used as index registers. Registers 12 through 15 can be used as base registers. Any of the 16 registers could be used as a stack pointer for the SJS & URS instructions (stack jump subroutine & unstack return subroutine), but only register 15 was used as the stack pointer for the PSHM & POPM instructions (push multiple & pop multiple). The computer has instructions for 16, and 32-bit binary arithmetic, as well as 32 and 48 bit floating point. I/O is generally via the I/O instructions (XIO and VIO), which have a separate 216 16-bit word address space and may have a specialized bus.

With the release of the Notice 4 revision to the standard on July 31, 1996 MIL-STD-1750A was declared inactive for new military projects in the USA. However, both the Indian Space Research Organisation and the Chinese aerospace industry continue to use the 1750 for new projects.

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