Template:Infobox CPU series
Appearance
[[File:{{{image}}}|frameless|alt={{{alt}}}]] | |
Launching | {{{launching}}} |
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Launched | {{{launched}}} |
Discontinued | {{{discontinued}}} |
Designed by | {{{designedby}}} |
Manufactured by |
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Fabrication process |
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Codename(s) |
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Platform(s) |
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Branding | |
Brand name(s) | {{{branding}}} |
Generation | {{{generation}}} |
Socket(s) |
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Instructions & Architecture | |
Instructions set | {{{instructions-set}}} |
Instructions | {{{instructions}}} |
Extensions |
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Core architecture | {{{core-arch}}} |
P-core architecture | {{{p-core-arch}}} |
E-core architecture | {{{e-core-arch}}} |
Cores | |
CCD codename | {{{ccd-codename}}} |
Core count | Up to {{{core-count}}} |
Peak core clock | Up to {{{peak-clock}}} {{{peakclock-unit}}} |
L1 cache | {{{l1-cache}}} |
L2 cache | {{{l2-cache}}} |
L3 cache | {{{l3-cache}}} |
P-core L0 cache | {{{p-l0-cache}}} |
P-core L1 cache | {{{p-l1-cache}}} |
E-core L1 cache | {{{e-l1-cache}}} |
P-core L2 cache | {{{p-l2-cache}}} |
E-core L2 cache | {{{e-l2-cache}}} |
P-core L3 cache | {{{p-l3-cache}}} |
E-core L3 cache | {{{e-l3-cache}}} |
Graphics | |
Graphics architecture | {{{graphics-arch}}} |
Model(s) |
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Compute Units | Up to {{{cu-count}}} CUs |
Execution Units | Up to {{{eu-count}}} EUs |
Xe Cores | Up to {{{xe-count}}} Xe Cores |
Peak graphics clock | {{{graphics-clock}}} {{{graphics-clockunit}}} |
NPU | |
Architecture | {{{npu-arch}}} |
TOPS | {{{npu-tops}}} |
Clock speed | {{{npu-clock}}} {{{npu-clockunit}}} |
Memory Support | |
Type | {{{memory-type}}} |
Memory channels | {{{memory-channels}}} |
Maximum capacity | {{{amountmemory}}} |
I/O | |
PCIe support | {{{pcie-support}}} |
PCIe lanes | {{{pcie-lanes}}} |
CXL support | {{{cxl-support}}} |
UPI links | {{{upi-links}}} |
DMI version | {{{dmi-version}}} |
HyperTransport version | {{{ht-version}}} |
History | |
Predecessor | {{{predecessor}}} |
Variant | {{{variant}}} |
Successor | {{{successor}}} |
Usage
[edit]{{Infobox CPU series
| name = <!-- Name of CPU series, following the name of the article -->
| image = <!-- An image to show in the infobox -->
| caption = <!-- A caption for the image -->
| alt = <!-- Mouse over text for the image -->
| launching = <!-- Use if a CPU series has not yet launched but its official release date is known -->
| launched = <!-- Use for the official release date for a CPU series after it has been released, not announced -->
| discontinued = <!-- Date for when the CPU series was discontinued -->
| designedby = <!-- Name of company who designed the CPU series, e.g. Intel, AMD -->
| manuf1 = <!-- (1..9) Name of company who manufactures the CPU series, e.g. TSMC, Samsung, GlobalFoundries -->
| process1 = <!-- (1..9) Semiconductor fabrication process, e.g. TSMC N7, Intel 14nm -->
| codename1 = <!-- (1..5) Official codename for the CPU series, e.g. Raphael, Vermeer, ADL, MTL -->
| platform1 = <!-- (1..5) Platform type, e.g. desktop, mobile, server -->
<!------------------ Branding ------------------->
| branding = <!-- Brand names used by processor series, e.g. Core, Xeon, Ryzen -->
| generation = <!-- Generation number, e.g. 5th Generation, 10th Generation, Series 1 -->
| socket1 = <!-- (1..9) CPU socket(s) used by the CPU series, e.g. LGA 1700, AM4, AM5, LGA 4677 -->
<!------------------ Instructions & Architecture ------------------->
| instructions-set = <!-- e.g. x86, ARM -->
| instructions = <!-- e.g. x86-64, AMD64, ARM64 -->
| extensions1 = <!-- (1..5) e.g. SSE, AVX2, AVX-512 -->
| core-arch = <!-- Codename for the architecture used by the CPU series, e.g. Zen 3, Zen 4, Skylake, Sunny Cove -->
| p-core-arch = <!-- Codename for the P-cores used by the CPU series, e.g. Golden Cove, Raptor Cove, Redwood Cove -->
| e-core-arch = <!-- Codename for the E-cores used by the CPU series, e.g. Gracemont, Crestmont, Skymont -->
<!------------------ Cores ------------------->
| core-codename1 = <!-- (1..9) Codename(s) for the CPU cores -->
| ccd-codename = <!-- Codename(s) for the Core Complex Die (CCD) on applicable AMD Ryzen and Epyc CPU series -->
| core-count = <!-- Number of cores (e.g. Up to 16 cores) -->
| peak-clock = <!-- Peak clock rate number, e.g. Up to 5.6 -->
| peakclock-unit = <!-- Peak clock rate unit, e.g. MHz or GHz -->
| l1-cache = <!-- Amount of L1 cache (per core) -->
| l2-cache = <!-- Amount of L2 cache (per core) -->
| l3-cache = <!-- Amount of L3 cache -->
| p-l0-cache = <!-- For Intel P-cores, amount of L0 cache (per P-core) -->
| p-l1-cache = <!-- For Intel P-cores, amount of L1 cache (per P-core) -->
| e-l1-cache = <!-- For Intel E-cores, amount of L1 cache (per E-core) -->
| p-l2-cache = <!-- For Intel P-cores, amount of L2 cache (per P-core) -->
| e-l2-cache = <!-- For Intel E-cores, amount of L2 cache (per E-core cluster) -->
| p-l3-cache = <!-- For Intel P-cores, amount of L3 cache (per P-core) -->
| e-l3-cache = <!-- For Intel E-cores, amount of L3 cache (per E-core cluster) -->
<!------------------ Graphics ------------------->
| graphics-arch = <!-- Graphics architecture used by the CPU's integrated graphics -->
| gpu-model1 = <!-- (1..9) Name of GPU models featured, e.g. UHD 770, UHD 630, 780M -->
| cu-count = <!-- Number of Compute Units (CUs) for AMD graphics, e.g. Up to 12 CUs -->
| xe-count = <!-- Number of Xe cores for Intel Arc graphics, e.g. Up to 8 X<sup>e</sup>-LPG cores -->
| eu-count = <!-- Number of Execution Units (EUs) for Intel graphics, e.g. Up to 24 EUs -->
| graphics-clock = <!-- Peak graphics clock for the integrated GPU, e.g. Up to 2100 MHz -->
| graphics-clockunit =
<!------------------ NPU ------------------->
| npu-arch = <!-- e.g. XDNA, XDNA 2, NPU 3720 -->
| npu-tops = <!-- Number of TOPs performance for the NPU only, not the combined TOPs for the CPU, GPU and NPU -->
| npu-clock =
| npu-clockunit =
<!------------------ Memory Suppport ------------------->
| memory-type = <!-- Supported memory types, e.g. DDR3, DDR4, DDR5 -->
| memory-channels = <!-- Number of memory channels, e.g. 2 channels, 4 channels, 8 channels -->
| amountmemory = <!-- Maximum amount of memory supported, e.g. Up to 256{{nbsp}}GB, Up to 2{{nbsp}}TB -->
<!------------------ I/O ------------------->
| pcie-support = <!-- e.g. PCIe 3.0, PCIe 4.0, PCIe 5.0 -->
| pcie-lanes = <!-- Lanes provided by the CPU, not the PCH, e.g. 128 PCIe 5.0 lanes -->
| cxl-support = <!-- e.g. CXL 1.1, CXL 2.0 -->
| upi-links =
| dmi-version = <!-- Direct Media Inferface (DMI) version for Intel CPUs -->
| ht-version = <!-- HyperTransport version -->
| ht-speeds =
<!------------------ History ------------------->
| predecessor = <!-- What CPU series came before -->
| variant = <!-- Similar or related CPU series that is classified as part of the same generation or uses the same architecture -->
| successor = <!-- What CPU series came after -->
}}
Examples
[edit]Ryzen 7000 Series
[edit]Launched | September 27, 2022 |
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Designed by | AMD |
Manufactured by | |
Fabrication process | |
Codename(s) |
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Platform(s) |
|
Branding | |
Brand name(s) | Ryzen |
Socket(s) | |
Instructions & Architecture | |
Instructions set | x86 |
Instructions | |
Core architecture | Zen 4 |
Cores | |
Core codename | Persephone |
CCD codename | Durango |
Core count | Up to Up to 16 cores |
Peak core clock | Up to Up to 5.7 GHz |
L1 cache | 64 KB (per core):
|
L2 cache | 1 MB (per core) |
L3 cache | 32 MB (per CCD) |
Graphics | |
Graphics architecture | RDNA 2 |
Model(s) |
|
Compute Units | Up to 2 CUs |
Peak graphics clock | Up to 2100 MHz |
Memory Support | |
Memory channels | 2 channels |
I/O | |
PCIe support | PCIe 5.0 |
History | |
Predecessor | Ryzen 6000 series |
Successor | Ryzen 8000 series |
{{Infobox CPU series
| name = Ryzen 7000 Series
| image = AMD Ryzen 9 7900X.jpg
| caption = AMD Ryzen 9 7900X processor
| alt =
| launching =
| launched = {{start date|2022|09|27}}
| discontinued =
| designedby = [[Advanced Micro Devices|AMD]]
| manuf1 = [[TSMC]]
| process1 = [[TSMC]] [[5 nm process|N5]]
| process2 = [[TSMC]] [[7 nm process|N6]]
| codename1 = Raphael
| codename2 = Raphael-X
| platform1 = Desktop
<!------------------ Branding ------------------->
| branding = [[Ryzen]]
| generation = <!-- Generation number, e.g. 5th Generation, 10th Generation -->
| socket1 = [[Socket AM5]]
<!------------------ Architecture and Instructions ------------------->
| instructions-set = [[x86]]
| instructions = {{hlist|[[x86-64]]|[[x86-64|AMD64]]}}
| extensions = <!-- e.g. SSE, AVX2, AVX-512 -->
| core-arch = [[Zen 4]]
<!------------------ Specifications ------------------->
| core-codename = Persephone
| ccd-codename = Durango
| core-count = Up to 16 cores
| peak-clock = Up to 5.7
| peakclock-unit = GHz
| l1-cache = 64{{nbsp}}KB (per core): <br /> {{bulleted list|32{{nbsp}}KB instructions|32{{nbsp}}KB data}}
| l2-cache = 1{{nbsp}}MB (per core)
| l3-cache = 32{{nbsp}}MB (per {{abbr|CCD|Core Complex Die}})
| memory-support = [[DDR5 SDRAM|DDR5]]
| memory-channels = 2 channels
| pcie-support = [[PCI Express#PCI Express 5.0|PCIe 5.0]]
<!------------------ Integrated Graphics ------------------->
| graphics-arch = [[RDNA 2]]
| gpu-model1 = Radeon Graphics
| cu-count = 2
| graphics-clock = Up to 2100 MHz
<!------------------ History ------------------->
| predecessor = Ryzen 6000 series
| successor = Ryzen 8000 series
}}
Alder Lake
[edit]Launched | November 4, 2021 |
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Designed by | Intel |
Manufactured by | |
Fabrication process | |
Codename(s) |
|
Platform(s) |
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Branding | |
Brand name(s) | |
Generation | 12th Generation |
Socket(s) |
|
Instructions & Architecture | |
Instructions set | x86 |
Instructions | x86-64 |
Extensions | |
P-core architecture | Golden Cove |
E-core architecture | Gracemont |
Cores | |
Core count | Up to 16 cores:
|
Peak core clock | Up to Up to 5.5 GHz |
P-core L1 cache | 80 KB (per core):
|
E-core L1 cache | 96 KB (per core):
|
P-core L2 cache | 2 MB (per core) |
E-core L2 cache | 2 MB (per cluster) |
P-core L3 cache | 3 MB (per core) |
E-core L3 cache | 3 MB (per cluster) |
Graphics | |
Graphics architecture | Iris Xe |
Model(s) |
|
Execution Units | Up to 96 EUs |
Peak graphics clock | Up to 1550 MHz |
Memory Support | |
Type | DDR4-3200 DDR5-4800 |
Memory channels | 2 channels |
Maximum capacity | 256 GB |
I/O | |
PCIe support | PCIe 5.0 |
PCIe lanes | 16 PCIe 5.0 lanes 4 PCIe 4.0 lanes |
History | |
Predecessor | Rocket Lake |
Successor | Raptor Lake |
{{Infobox CPU series
| name = Alder Lake
| image = 2023 Intel Core i7 12700KF (5).jpg
| caption = Intel Core i7-12700KF
| alt =
| launched = {{start date|2021|11|04}}
| designedby = [[Intel]]
| manuf1 = [[Intel]]
| process1 = [[10 nm process|Intel 7]]
| codename = ADL
| platform1 = Desktop
| platform2 = Mobile
<!------------------ Branding ------------------->
| branding = {{ubl |[[Intel Core|Core]] |[[Pentium]] |[[Celeron]] |Intel Processor}}
| generation = 12th Generation
| socket1 = [[LGA 1700]]
| socket2 = BGA{{nbsp}}1774
| socket3 = BGA{{nbsp}}1964
<!------------------ Instructions & Architecture ------------------->
| instructions-set = [[x86]]
| instructions = [[x86-64]]
| extensions = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Intel SHA extensions|SHA]], [[Trusted Execution Technology|TXT]], [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]], [[FMA3]], [[Advanced Vector Extensions#AVX-VNNI|AVX-VNNI]], [[VT-x]], [[VT-d]]
| p-core-arch = [[Golden Cove]]
| e-core-arch = [[Gracemont]]
<!------------------ Specifications ------------------->
| core-count = 16 cores: <br /> {{bulleted list|Up to 8 P-cores|Up to 8 E-cores}}
| peak-clock = Up to 5.5
| peakclock-unit = GHz
| p-l1-cache = 80{{nbsp}}KB (per core): <br /> {{bulleted list|32{{nbsp}}KB instructions|48{{nbsp}}KB data}}
| e-l1-cache = 96{{nbsp}}KB (per core): <br /> {{bulleted list|64{{nbsp}}KB instructions|32{{nbsp}}KB data}}
| p-l2-cache = 2{{nbsp}}MB (per core)
| e-l2-cache = 2{{nbsp}}MB (per cluster)
| p-l3-cache = 3{{nbsp}}MB (per core)
| e-l3-cache = 3{{nbsp}}MB (per cluster)
<!------------------ Memory Support ------------------->
| memory-type = [[DDR4 SDRAM|DDR4]]-3200 <br/> [[DDR5 SDRAM|DDR5]]-4800
| memory-channels = 2 channels
| amountmemory = 256{{nbsp}}GB
<!------------------ I/O ------------------->
| pcie-support = [[PCI Express#PCI Express 5.0|PCIe 5.0]]
| pcie-lanes = 16 [[PCI Express#PCI Express 5.0|PCIe 5.0]] lanes <br/> 4 [[PCI Express#PCI Express 4.0|PCIe 4.0]] lanes
<!------------------ Integrated Graphics ------------------->
| graphics-arch = [[Intel Xe|Iris X<sup>e</sup>]]
| gpu-model1 = UHD 730
| gpu-model2 = UHD 770
| eu-count = 96
| graphics-clock = Up to 1550 MHz
<!------------------ History ------------------->
| predecessor = [[Rocket Lake]]
| successor = [[Raptor Lake]]
}}
EPYC 9004 Series
[edit]Launched | November 10, 2022 |
---|---|
Designed by | AMD |
Manufactured by | |
Fabrication process | |
Codename(s) |
|
Platform(s) |
|
Branding | |
Brand name(s) | EPYC |
Generation | 4th Generation |
Socket(s) | |
Instructions & Architecture | |
Instructions set | x86 |
Instructions | |
Core architecture | Zen 4 Zen 4c |
Cores | |
CCD codename | Durango |
Core count | Up to Up to:
|
L1 cache | 64 KB (per core):
|
L2 cache | 1 MB (per core) |
L3 cache | 32 MB (per CCD) |
Memory Support | |
Type | DDR5-4800 |
Memory channels | 12 channels |
Maximum capacity | Up to 6 TB (per socket) |
I/O | |
PCIe support | PCIe 5.0 |
PCIe lanes | 128 PCIe 5.0 lanes 12 PCIe 3.0 lanes |
CXL support | CXL 1.1+ Type 3 |
History | |
Predecessor | EPYC 7003 ("Milan") |
Variant | EPYC 8004 ("Siena") |
Successor | EPYC 9005 ("Turin") |
{{Infobox CPU series
| name = EPYC 9004 Series
| image =
| caption =
| alt =
| launched = {{start date|2022|11|10}}
| discontinued =
| designedby = [[Advanced Micro Devices|AMD]]
| manuf1 = [[TSMC]]
| process1 = [[TSMC]] [[5 nm process|N5]]
| process2 = [[TSMC]] [[7 nm process|N6]]
| codename1 = Genoa
| codename2 = Genoa-X
| codename3 = Bergamo
| platform1 = Server
<!------------------ Branding ------------------->
| branding = [[EPYC]]
| generation = 4th Generation
| socket1 = [[Socket SP5]]
<!------------------ Instructions & Architecture ------------------->
| instructions-set = [[x86]]
| instructions = {{hlist|[[x86-64]]|[[x86-64|AMD64]]}}
| extensions = <!-- e.g. SSE, AVX2, AVX-512 -->
| core-arch = [[Zen 4]] <br/> [[Zen 4#Zen 4c|Zen 4c]]
<!------------------ Specifications ------------------->
| core-codename1 = Persephone
| ccd-codename = Durango
| core-count = : <br/> {{bulleted list|96 Zen 4 cores|128 Zen 4c cores}}
| peak-clock =
| peakclock-unit = GHz
| l1-cache = 64{{nbsp}}KB (per core): <br /> {{bulleted list|32{{nbsp}}KB instructions|32{{nbsp}}KB data}}
| l2-cache = 1{{nbsp}}MB (per core)
| l3-cache = 32{{nbsp}}MB (per {{abbr|CCD|Core Complex Die}})
<!------------------ Memory Support ------------------->
| memory-type = [[DDR5 SDRAM|DDR5]]-4800
| memory-channels = 12 channels
| amountmemory = Up to 6{{nbsp}}TB (per socket)
<!------------------ I/O ------------------->
| pcie-support = [[PCI Express#PCI Express 5.0|PCIe 5.0]]
| pcie-lanes = 128 [[PCI Express#PCI Express 5.0|PCIe 5.0]] lanes <br/> 12 [[PCI Express#PCI Express 3.0|PCIe 3.0]] lanes
| cxl-support = [[Compute Express Link|CXL 1.1+]] Type 3
<!------------------ History ------------------->
| predecessor = EPYC 7003 <br/> ("Milan")
| variant = EPYC 8004 <br/> ("Siena")
| successor = EPYC 9005 <br/> ("Turin")
}}