Talk:Transistor–transistor logic/Archive 2

Archive 1

Archive 2

Current sinking logic

I would like to know what this vague sentence "TTL is a current-sinking logic since a small current must be drawn from inputs to at logic 0 level" means: TTL is a current-sinking logic since "the current that must be drawn from the inputs is small" or "the current that must be drawn from the inputs must to be small" or something else? And also "...from inputs to at logic 0 level..."? But is the current really small? To say small or big, we have to compare it with another current, in this case, with the current at logical "1". When, is the drawn current (1.1 mA) less than the injected current (40 μA)? No, it is almost 30 times bigger... Circuit dreamer (talk, contribs, email) 18:14, 14 October 2010 (UTC)

OK, so how to explain this *compactly* without going on for a full screen of text? I thought it was adequate. What do you propose as an alternative wording? How much precision does the reader really need to understand that some current must be drawn out of the input to maintain a logic 0 voltage level? Later on we give 1.1 mA and 40 uA, take out the word "small" if you think it confuses the reader. --Wtshymanski (talk)

A nominal current level is given in the explanation of current sinking inputs. My complaint with this article is that it has a lot of fractured English, making it difficult to read. An example from the same paragraph- "The input base-emitter junction deprives all the base current of the output transistor (the current is steered from the base..." Maybe an attempt at too much explanation with a simplified schematic. The second transistor has no bias resistor so no current is supplied to that node anyway. It would just float up due to leakage currents. Zen-in (talk) 05:06, 15 October 2010 (UTC)

See if you like my cleanup attempt. I took out a paragraph that didn't make sense to me, too. If someone can explain it and support it by sources, of course we can have it back and work on clarifying it. Dicklyon (talk) 05:32, 15 October 2010 (UTC)

Dicklyon, IMO you have gone too far in cleaning up the interfacing section. These situations are very important for TTL circuit design; so, they deserve to be included in the article. This morning, I posed the problem to my students on the whiteboard in the laboratory of digital circuits (see the picture on the right). They tried to find answers to my questions in Wikipedia but they did not manage since the answers were removed:) Well, let's discuss these considerations here. Circuit dreamer (talk, contribs, email) 14:32, 15 October 2010 (UTC)

1. TTL with output logical "1" driving a few TTL inputs (belonging to one gate or to separate gates)

In this case (see the green currents in the picture), the input multiple-emitter transistor of the next stage operates in a reverse-active mode where the emitter and collector are swapped. Every emitter-collector junction (every TTL input) acts as a transistor current sink "pulling" a small current (about 40 μA ) from the upper transistor V3 of the previous stage. All these emitter-collector junctions (current-stable elements) are connected in parallel; so, their currents are summed. Thus, the total current is proportional to the number of the parallel connected inputs.

The problem is that it needs even more to make it correct and consistent. I don't see how it's worth it, but maybe if you have sources that teach it this way we could look at what they say, and include this material. The previous paragraph says the inputs will float to a logic 1 level, which means the 40 μA is really a voltage-dependent current that will go to 0 at some voltage; so a huge fanout will but into the margin when it can't supply 40 μA per input, but is that really the fanout limit? I thought the fanout limit was the current sinking ability. Do you have a source that supports this as the thing that limits fanout? Dicklyon (talk) 18:19, 15 October 2010 (UTC)

I have good sources from my student years but they are not in English. They give me a good basis for my reasoning but I do not rely on them completely... I hope we will find reputable sources treating this topic; until then we have to rely only on our human reasoning and common sense:)

The TTL input behaves very strange and vagarious when the input voltage increases from zero to V_CC. We may get a notion about this odd behavior by tracking the TTL input IV curve through this change (sorry, I have not found it on the web) and by considering where the input current flows.

In the beginning (V_IN = 0 - 0.4 V), the base-emitter junction of the input multiple-emitter transistor V1 is forward biased; so, the input resistance is linear and completely determined (4 k) by the base resistor R₁. Then (V_IN = 0.4 - 1.4 V), V2 diverts a small part of the input current through its base-emitter junction and switches on. After (V_IN = 1.4 - 1.5 V), V4 base-emitter junction becomes forward-biased as well and begins drawing away a significant part of the input current. As a result, the current changes vigorously; the dynamic input resistance is very small and the input behaves as a voltage-stable non-linear element. At V_IN > 1.5 V, V1 base-emitter junction becomes zero biased and the current becomes zero; the input resistance is infinite. After that point, the base-emitter junction becomes even backward biased while its base-collector junction is forward biased. This is the so called reverse-active mode, in which the collector and emitter are swapped. But note it is undesired here since small current flows from the "collector" (actually, the emitter) to the "emitter" (actually, the collector). We do not need such a "transistor" during the whole 0-to-V_CC transition; we need only two humble diodes - an input backward-biased one and an output forward-biased one (so, DL and DTL do not have such a problem). This "collector" current is small (about 40 μA) as the transistor's "ß" is intentionally made very small (ß = I_"c"/I_b << 1) so this is an attenuating transistor:) Its "collector" current is relatively constant since its "collector"-"emitter" junction behaves as a current-stable non-linear resistor (like the ordinary amplifying transistor). As a generalization, the TTL input transformations are:

1. A real voltage source with internal ohmic resistance R_IN = R₁ (a logical "0" is applied at the input).

2. A real voltage source with internal dynamic resistance R_IN < R₁.

3. An almost ideal voltage source with internal dynamic resistance R_IN = 0.

4. A disconnected voltage source.

5. An almost ideal current sink with infinite internal dynamic resistance (a logical "1" is applied at the input).

You have said above ...the 40 μA is really a voltage-dependent current that will go to 0 at some voltage... Yes, it is true - the input current becomes zero at V_IN = 1.5 V and then changes its direction. But note this point is out of the operating range and it is not admissible. Circuit dreamer (talk, contribs, email) 20:59, 17 October 2010 (UTC)

2. TTL with output logical "0" driving a few TTL inputs...

...belonging to one gate...

Now, the forward biased emitter-base junctions (voltage-stable elements) of the input multiple-emitter transistor are connected in parallel. The total current drawn from the previous stage is about 1.1 mA for a standard TTL gate and it does not depend on the number of the parallel connected inputs (emitter-base junctions). This current is equally distributed between the junctions.

...belonging to separate gates.

In this case (see the blue currents in the picture), the base resistors of the separate gates are connected in parallel. The total current drawn from the previous stage is a sum of the separate input currents of 1.1 mA and it is proportional to the number of the parallel connected inputs. Circuit dreamer (talk, contribs, email) 14:32, 15 October 2010 (UTC)

I had missed the funny distinction of "belonging to one gate", which I see now really means belonging to one input transistor. From the outside of a package, no such assumptions can be reliably made, and that special case is of no practical importance. Why would you bring it up? In general, long-winded unsourced explanations are not appropriate for wikipedia; if we can't verify them in sources, as opposed to arguing about what's right, they shouldn't be there. Dicklyon (talk) 18:19, 15 October 2010 (UTC)

Zen-in, AND DL, AND DTL and (to some extent) TTL are current-sinking logic but their inputs are current-sourcing because of the internal pull-up resistor. Dually, OR DL, OR DTL, RTL and DCTL are current-sourcing logic but their inputs are current-sinking because of the internal pull-down resistor. IMO these descriptive names are misleading since they are based on the present circuit mode, not on the inherent circuit input properties. They assume that two identical logic gates are connected consecutively (e.g., TTL drives TTL or RTL drives RTL). In these arrangements, "TTL current-sinking logic" means that a TTL output (at logical "0") sinks current from the next TTL input; "RTL current-sourcing logic" means that an RTL output (at logical "1") sources current to the next RTL input. But if TTL drives RTL, this current-sinking gate will source current to the next current-sourcing gate; if RTL drives TTL, this current-sourcing gate will sink from the next current-sinking gate. The problem is that the output stages of logic gates are almost symmetrical; they can both source and sink current and they can operate as both sourcing and sinking. In contrast, their inputs are asymmetrical; they can either source or sink current. So, it would be better if TTL was named current-sourcing logic because of its sourcing inputs and RTL - current-sinking logic because of its sinking inputs. Circuit dreamer (talk, contribs, email) 18:00, 15 October 2010 (UTC)

This paragraph doesn't seem to be about the article or how to improve it. Dicklyon (talk) 18:23, 15 October 2010 (UTC)

This was an essay about current-sinking/sourcing terminology. I suggest to move this discussion and this more general topic to Logic gate. Circuit dreamer (talk, contribs, email) 19:11, 15 October 2010 (UTC)

Zen-in, please, explain what you mean when saying: "The second transistor has no bias resistor so no current is supplied to that node anyway. It would just float up due to leakage currents." What is the "second transistor"? What is this node? What will float - the transistor or the node? What are these leakage currents? Where they flow? Circuit dreamer (talk, contribs, email) 18:06, 15 October 2010 (UTC)

The picture next to "TTL with simple output stage" is missing a bias resistor on the base of the output stage. Most TTL data sheets draw the schematic that way but it is a simplification and not useful for describing the circuit. Educational textbooks like Electronic Principles Physics, Models, and Circuits by Gray and Searle, page 870, shows a similar circuit but includes the bias resistor. Just as it is a mistake to consider a transistor as being two back to back diodes it is also a mistake to consider the multiple emitters of a TTL NAND input to be the same as the diodes of diode logic. The latter former are junctions on a transistor and don't "steer" current. They are carefully designed so that none will hog the current when all are conducting. Logic families are not usually mixed. There are all kinds of special cases and considerations. It doesn't make any sense to make new rules of terminology based on the supposition that logic families can be arbitrarily mixed. The paragraphs under "structure and operation"(?) are bloated and very confusing to read. It would be better to have one schematic that more closely represents a TTL NAND gate. It should have the base bias resistor and a realistic totem pole stage. That would allow a more concise explanation section using generally accept terminology. It is very good that Circuit dreamer is enthusiastically introducing young people in Sofia to electronics. But there is the appearance that his employment as an instructor and his Wikipedia activities are too closely linked. Zen-in (talk) 05:23, 16 October 2010 (UTC)

I have not yet realized the need of the "missing biasing resistor on the base of the output stage" but I will ask tomorrow my students to help me to see it:)

My students already know that "it is a mistake to consider a transistor as being two back to back diodes" but only in the case of amplifying transistor stages; it is not only completely acceptable but extremely useful "to consider the multiple emitters of a TTL NAND input to be the same as the diodes of diode logic"; they "are junctions on a transistor and don't "steer" current"; they "are carefully designed so that none will hog the current when all are conducting". To convince themselves, last week, at the beginning of TTL lab, they conducted interesting "current-steering" experiments with three identical LEDs supplied by current. First, they connected a LED in parallel to another LED (see the picture on the left) and saw that the two parallel connected LEDs were lighted (the third was connected in series to them). Then, they connected a LED in parallel to two connected in series LEDs (see the picture on the right) and saw how the two series connected LEDs were extinguished. Circuit dreamer (talk, contribs, email) 22:19, 17 October 2010 (UTC)

Your experiment doesn't prove anything about TTL gates and as usual you are misusing the discussion page by filling it with content that is unrelated to the edits of this article. You have been warned several times about this kind of behavior. I am surprised that you persist in this. Zen-in (talk) 04:01, 18 October 2010 (UTC)

I am surprised that you cannot see the so simple but brilliant ideas behind circuits. Circuit dreamer (talk, contribs, email) 05:26, 18 October 2010 (UTC)

You are mistaken. Your LED experiment demonstrate current hogging but it is not how TTL inputs work. Two LEDs need twice as much voltage across them to conduct. The one LED that is in parallel with them turns on instead. If two PN junctions have closely matched I-V curves they will both conduct the same current when they are in parallel. That is what TTL manufacturers did when they made TTL chips. If the junctions were not matched and there was current hogging the turn on and turn off time of the gate would change depending on what inputs were changing and the parts would be junk. When you are able to make a transistor from two discrete diodes let me know. Zen-in (talk) 05:52, 18 October 2010 (UTC)

I agree with Zen-in. Circuit Dreamer, you waste too much of our time by the amount of work you create for those of us who want the article to remain finite and well sourced. Cut out the essays, in both article and talk pages. You are starting to remind me too much of User:Brews ohare. Dicklyon (talk) 07:16, 18 October 2010 (UTC)

Zen-in, sorry but it is you who are mistaken. The LED experiment above demonstrates exactly how TTL inputs work and also how the output totem-pole stage works. The one LED represents one base-emitter junction of the multiple-emitter transistor V1; the two connected in series LEDs represent V1 base-collector junction and V2 base-emitter junction. LEDs are used instead ordinary diodes since they indicate the current flowing through them; so, there is no need of connecting ammeters that will also introduce error with their internal resistance. Your explanation about how they work is exactly the same as my explanations in the article about this current steering or, if you prefer, current dogging phenomenon (they are the same). This was the main problem in 60's - how to divert the current from T2 input to the input source at input logical "0" - that DTL and TTL designers solved by connecting in parallel voltage-stable elements with different thresholds (one junction in parallel to two series connected junctions). The problem that you have posed above is another problem - how to equalize the input currents during the transition around 1.4 V; they solved it by matching V1 input base-emitter junctions.

There is no need of making a transistor from two discrete diodes. The multiple-emitter junctions are used as diodes: the base-emitter junctions - as diode switches with a logic function; the base-collector junction - as a "shifting" voltage-stable element. Circuit dreamer (talk, contribs, email) 15:32, 19 October 2010 (UTC)

As Dicklyon and others have stated many times your long-winded dissertations on talk pages are disruptive. I moved this latest discussion to your talk page so that it can be deleted from the TTL talk page. You claim that the inputs of a TTL gate are electrically the same as multiple diodes feeding into one emitter. Can you provide any qualified references that this is so? If you are so fortunate as to have a copy of the book I referred to earlier (Electronic Principles Physics, Models, and Circuits by Gray and Searle), you will see on page 870 that the schematic of a TTL gate is drawn with multiple transistors that have their Bases and Collectors tied together. The inputs of this TTL gate schematic are the individual emitters, that are not tied together. A multiple emitter transistor is equivalent to multiple transistors that have their bases and collectors in common. With the same bias on all the gates bases, they will all have the same emitter current when the emitters are connected to ground (through a resistor or the bottom of a totem pole stage that is switched on). You can dispute this all you want but this textbook has been in print for over 40 years and has been used by many EE faculties. The authors, Paul E. Gray and Campbell L. Searle are highly respected. They were both members of the Semiconductor Electronics Education Committee, which developed pedagogical standards for teaching solid state electronics 45-50 years ago. You would be doing your students a great service by acquiring and "scrutinizing" some of their many publications. Zen-in (talk) 03:09, 20 October 2010 (UTC) (copied here from User talk:Circuit dreamer by Circuit dreamer)

I have copied this section over to Circuit dreamer's talk page and added what are hopefully final notes on this subject. If someone would go ahead and delete the above disruptive content it would be appreciated by almost everyone. Zen-in (talk) 03:11, 20 October 2010 (UTC)

Can truth be disruptive? I have never claimed that "the inputs of this TTL gate schematic are not individual emitters" or that "they are tied together". Instead, I (and not only I) claim the TTL inputs are base-emitter junctions that behave as diodes with the only purpose to make a connection with the previous DL and with current steering phenomenon. The bases of these base-emitter junctions are joined by the common base like the anodes of the input DL diodes. So, think of this metaphorical comparison as of a kind of a diode analogy. I have also written many times and explained in detail why "TTL inputs have the same emitter current when the emitters are connected to ground". What do you want to say repeating this assertion again and again?

You have urged others to delete my considerations here. But can you realize that I have written them just for you since you cannot understand even the simplest circuit concepts? And what will remain here after such a deletion? Your "saying nothing" thoughts? Striking a balance, only one of your insertions deserves attention and can be inserted in the article - about matching the input base-emitter junctions. Circuit dreamer (talk, contribs, email) 04:30, 20 October 2010 (UTC)

Fundamental TTL gate

I have reconstructed the section about TTL implementation since the last edit was poor. Here are my considerations.

• There is no structure and hierarchy.

• The sentence "This configuration has a low impedance..." is true only at input logical one.

• "...and offers a lot of isolation between the inputs" is not a unique TTL characteristic; it is inherent for the humble DTL as well.

• The sentence "When the inputs are all at a voltage above the turn on voltage (logical "1"), no current flows across the base emitter junctions and the input transistor is in cut-off mode" is not true. In this case, the emitter of the input n-p-n transistor is more positive than its collector as though the collector and emitter are swapped. The transistor operates in the so called reverse-active mode, in which small (about 10 μA) "collector" current flows. It sounds paradoxical but the passive DTL diode switches do not have this problem.

• There is no need to introduce any biasing in this generic (conceptual, fundamental, simplified) circuit diagram. It works excellent without any biasing since the base-emitter junction of the output transistor is forward-biased through the base resistor and the base–collector junction of the multiple-emitter transistor (see the article). So, the sentence "The output transistor conducts because it is biased on by a bias network not shown in the diagram" is redundant. Furthermore, the additional bias current will flow through the collector-emitter junction of the turned on multiple transistor and will add to the "conventional" input current; as a result, the current drawn at input logical one will increase and the input resistance will decrease. "...the bias network for the base of the output transistor establishes the turn on voltage of the gate" sounds strange. What is this "turn on voltage of the gate" and how the bias network can establish it? We can only guess what these highly respected authors tried to achieve in distant 60's by this additional biasing...

I have thoroughly considered this arrangement but I have not found sound reason for biasing. I have only noted that in the conventional TTL gate the output transistor is cut-off by connecting one base-emitter junction (0.7 V) in parallel to two connected in series junctions (1.4 V) whereas in the biased gate the same is made by connecting the collector-emitter junction (0 V) in parallel to one base-emitter junction (0.7 V). But I cannot see any benefit of this connection.

• I have left the presentation of the multiple-emitter transistor as a set of multiple transistors whose bases and collectors are tied together although it does not help understanding. Thinking of the multiple-emitter transistor as a set of diodes is quite better analogy. Circuit dreamer (talk, contribs, email) 16:02, 1 November 2010 (UTC)

You removed a very reputable citation and have replaced my edits with your idiosynchratic pov. You should find some references to back up your claims. Maybe the TTL gates you have been building circuits with are different from what is available here in California because your observations don't agree with what is commonly accepted. Zen-in (talk) 03:44, 2 November 2010 (UTC)

The citation is there. I have left your edits about presentation of multiple-emitter transistor as multiple transistors with bases and collectors tied together but seriously there is no need to introduce such detail as biasing in the fundamental TTL circuit diagram. Look at Tony Kuphaldt's lessons about TTL gates - "...the "steering" diode cluster marked "Q1" is actually formed like a transistor, even though it isn't used in any amplifying capacity..." It is not absolutely necessary to live in California to understand circuits. Circuit dreamer (talk, contribs, email) 20:54, 2 November 2010 (UTC)

I never said it was absolutely necessary to live in California to understand circuits - those are your words. However you have for some reason made a lot of bad assumptions whenever you have written about electronic circuits. In the case of TTL, it is a low impedance circuit; on the input and the output. Your statement that it has a low impedance only when it is not high is ludicrous and shows that you don't know how impedance is measured in circuits. That is something you should research. I know you don't believe in incremental analysis, Spice models, and electronic analysis math so I won't digress. The input stage of TTL is a Common base configuration which commonly accepted to have a low impedance input. But again I recall you saying that you don't believe a common base transistor amplifier really exists.

The last time I checked this article was about TTL, not DTL, so it is entirely valid to state characteristics about TTL here even if DTL circuits may have the same. The enhanced isolation characteristics of TTL is an important aspect and should not have been deleted.

Your confusion concerning basic semiconductor physics is even more evident in this statement: "In this case, the emitter of the input n-p-n transistor is more positive than its collector as though the collector and emitter are swapped. The transistor operates in the so called reverse-active mode, in which small (about 10 μA) "collector" current flows." When a transistor's base-emitter junction is reverse biased the transistor is in cut-off mode. 10 μA is a lot of leakage current; 50 nA is more typical (2N3904). What you are describing is not reverse-active mode. That happens when the collector and emitter are physically swapped, resulting in a transistor with a very low current gain and other useless properties.

In order to accurately describe the circuit operation a resistor needs to be added from V_CC to the Collector₁-Base₂ node. The circuit as drawn does not have any way of supplying enough collector current to equal what leaves the emitters. Are you trying to claim that transistor 2, when reverse biased will supply enough reverse leakage current through the base for the -.36 mA/emitter (7400) input drive condition when the inputs are low? As I recall you believe in Kirchoff's current law; so where do you think that current comes from?

Electronics is not a field where you can take artistic licence and make up rules as you go along. Zen-in (talk) 05:17, 3 November 2010 (UTC)

• TTL input has low resistance only at low input level: the static input resistance is Vlow/Iin = 0.8 V/1.1 mA ≈ 730 Ω; the differential input resistance is ΔVin/ΔIin ≈ 4 k (the resistance of the base resistor).

• TTL input has extremely high input resistance at high input level: the static input resistance is Vhigh/Iin = 3.5 V/10 μA = 350 kΩ; the differential input resistance is ΔVhigh/ΔIin → ∞ (the input behaves as a current source).

• The input stage of TTL is not a common-base configuration at all since the base of the input transistor is not connected to a steady voltage source.

• TTL gate has worse isolation characteristics than DTL since the base-emitter junctions of the multiple-emitter transistor draw some input current (10 - 50 μA). The anode-cathode junctions of the DTL input diodes draw only the extremely small 50 nA leakage current that you talk about.

• At high input voltage, the input transistor operates exactly in a reverse-active mode since its emitter is more positive than its collector and the base-collector junction is turned on, which means exactly that "its collector and emitter are physically swapped". Really, the base-emitter junction of the input transistor is reverse biased but its base-collector junction is forward-biased; so, the base-emitter junction acts as a base-collector one and the base-collector junction - as a base-emitter one.

• The sentence "When a transistor's base-emitter junction is reverse biased the transistor is in cut-off mode" is wrong here since the base-collector junction of the input transistor is forward-biased. The transistor would be cut-off if both the junctions were backward-biased.

• The sentence "10 μA is a lot of leakage current; 50 nA is more typical (2N3904)" is wrong and misleading here. "10 μA" is the "collector" current (i.e., the emitter current acting as a collector one) of the input transistor with forward-biased "base-emitter" junction (i.e., base-collector junction acting as a base-emitter one). "50 nA" that you talk about is the small leakage collector current (the reverse saturation current Is) of a cut-off transistor operating in a normal mode (with backward-biased base-emitter junction).

• There is no need of "a resistor to be added from V_CC to the Collector₁-Base₂ node" since a sufficient base current flows through the base resistor, the base–collector junction of the multiple-emitter transistor and the base-emitter junction of the second transistor: Ib = (Vcc - Vbc - Vbe)/Rb = (5 - 0.7 - 0.7)/4 = 0.9 mA. Even if β would only 25, the collector current of the second transistor will be a cool 22 mA (6 mA drawn from the collector resistor and 16 mA drawn from the maximum 10 next TTL inputs). BTW, I have thoroughly read the Buie's patent and TI 7401 datasheet but I have not found any notes about some useful biasing. Indeed, Buie have talked about some biasing but as something bad ("fault" or leakage between the positive rail and the base of the second transistor).

• The additional biasing resistor will increase the TTL input current at low input level.

Circuit dreamer (talk, contribs, email) 17:58, 5 November 2010 (UTC)

You are completely wrong. You don't know what happens when a transistor is in cut-off mode and if you think 50 nA reverse leakage current is wrong you should tell the manufacturers (2N3904) they have been misleading everyone for the last 40 some years. The impedance of active circuits is not measured with ohm meters. Good to hear you now believe common base amplifiers exist. Zen-in (talk) 04:44, 6 November 2010 (UTC)