Talk:Register-transfer level

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Link to Resistor–transistor logic?

If RTL-level design was ever used for RTL-logic design, and we could find a source to that effect, there might be a reason to imagine a relationship. But TTL and ECL and CMOS are more likely targets for it, and they're not linked, to let's not link the Resistor–transistor logic that's related only by initialism. Same from the other side(s). Dicklyon (talk) 02:29, 24 April 2008 (UTC)[reply]

Relationship between HDL and RTL

Is it correct to say that HDLs allow to express a digital circuit at the abstraction of RTL?
~~RTL is used in the logic design phase of the integrated circuit design cycle.~~
- Logic design redirects to Boolean algebra (logic) which is a mathematical term, not a engineering term. So what is meant with logic design phase?
  - changed this --64.2.143.12 (talk) 20:49, 9 April 2010 (UTC)[reply]
When designing digital integrated circuits with a hardware description language, the designs are usually engineered at a higher level of abstraction than transistor or gate level.
- Can someone define transistor level and gate level?

Thanks, --Abdull (talk) 23:17, 8 February 2010 (UTC)[reply]

Clock edge

The article says "...changes its state on each clock edge.". Shouldn't this be "...each rising clock edge." or "...each positive clock edge"? Ellingd (talk) 16:53, 2 March 2010 (UTC)[reply]

Correct, section changed. --82.132.248.221 (talk) 12:00, 10 April 2010 (UTC)[reply]

VHDL example

D latch operation: at the edge of a clock, input will be made available at the output. The example, however implies that the input function is synchronised.

Wrong

process(clk)
begin
    if rising_edge(clk) then
        D <= not Q;
    end if;
end process;

Right

D <= not Q;

process(clk)
begin
    if rising_edge(clk) then
        Q <= D;
    end if;
end process;

--Armandas j (talk) 15:11, 15 April 2010 (UTC)[reply]

Proposed merge with State of art power estimation techniques for RTL

"Power estimation" would make a good addition to this existing RTL page, would improve the sources for this topic, and neither page is big enough that a spinoff is necessary. — {{U|Technical 13}} ^{(e • t • c)} 14:24, 22 April 2015 (UTC)[reply]

Agreed and

Done Klbrain (talk) 21:25, 14 October 2017 (UTC)[reply]

This is the first time I've ready this page, and I have to say that the whole section on RTL power estimation seems strangely out of place on this page. 209.145.84.194 (talk) 12:51, 20 March 2024 (UTC)[reply]

Comparison with software compiler design

Coming from high level languages to verilog, my interest was piqued by paragraph 3, but I can make no sense of what it means. What kind of restrictions are there on verilog if one wants to do synthesis? 90.246.123.33 (talk) 09:47, 20 November 2024 (UTC)[reply]