Talk:I3C (bus)

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SPI is not more complicated?

“speeds common to more complicated buses such as the Serial Peripheral Interface (SPI).”

SPI does use more signals but SPI is often far simpler to use than I2C, as data is simply clocked in or out of the device by the host. I2C has addressing, multi-master capability etc. 2A02:C7C:CAFD:FF00:D4D9:48B8:C693:2E51 (talk) 22:31, 5 October 2023 (UTC)[reply]

Problem with HDR restart pattern in ternary modes

The following is WP:OR, but hopefully okay to discuss on a talk page.

The HDR restart pattern is defined as (I3C 1.0 §5.2.1.2), starting with SCL low and SDA high:

Falling edge on SDA
Rising edge on SDA
Falling edge on SDA
Rising edge on SDA
Rising edge on SCL

The later sections (I3C 1.0 §5.2.1.4) further require that the receiver must not observe three falling edges of SDA while SCL remains low (SCL must have been high at some point between step 1 of the pattern and the SDA falling edge before that), but that's not described clearly in the text. Even assuming this additional restriction, it seems it's possible to have a false detection.

Suppose that the SCL low-side driver (which controls the speed of falling edges) is particularly strong, and its high-side driver is particularly weak. The SDA drivers are intermediate in strength.

This means that any time a ternary symbol "0" is generated, which toggles both outputs simultaneously, the receivers see falling edges of SCL before the corresponding SDA edge, and rising edges after the SDA edge.

Suppose we start with SCL and SDA both high, then send bit triples 010 110. In a ternary mode, these are encoded as trit pairs 02 20. Given our driver speed discrepancies, this will be received as:

SCL falling edge (while SDA remins high) [first 0 trit first edge]
SDA falling edge (while SCL remins low) [first 0 trit second edge]
SDA rising edge (while SCL remins low) [first 2 trit]
SDA falling edge (while SCL remins low) [second 2 trit]
SDA rising edge (while SCL remins low) [second 0 trit first edge]
SCL rising edge (while SDA remains high) [second 0 trit second edge]

This is a valid HDR restart sequence, even with the additional pattern restriction.

If the SCL/SDA skew is deterministic (due to unbalanced trace capacitance), this can't happen, but there are several possible reasons why there could be asymmetry. Imbalanced drivers is just the simplest to describe. Unequal receiver thresholds or unequal pull-ups are other possibilities, as is crosstalk.

Does anyone else agree with this logic? 97.102.205.224 (talk) 03:26, 4 October 2024 (UTC)[reply]