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zz very partial view of high-level synthesis =

This page identifies synthesis with a subset of synthesis approaches from C. This is very far from a broad set of high-level synthesis approaches that exist. Other approaches use different languages; some are directly executable but much more declarative than C, some are not even directly executable in an obvious way. Sophisticated algorithms have been developed for synthesis and have been shown to be applicable to real-world examples. This article mentions none of these. —Preceding unsigned comment added by Vkuncak (talk • contribs) 10:26, 31 March 2010 (UTC)[reply]

zz very partial view of high-level synthesis =

This page identifies synthesis with a subset of synthesis approaches from C. This is very far from a broad set of high-level synthesis approaches that exist. Other approaches use different languages; some are directly executable but much more declarative than C, some are not even directly executable in an obvious way. Sophisticated algorithms have been developed for synthesis and have been shown to be applicable to real-world examples. This article mentions none of these. —Preceding unsigned comment added by Vkuncak (talk • contribs) 10:26, 31 March 2010 (UTC)[reply]

contradictions

This page is badly written, for instance the following phrase is both false and contradictoire:

"The starting point of a high level synthesis flow is ANSI C/C++/SystemC code that includes a bit-accurate class library."

How can you say that the code is high level if you use a bit-accurate library?

This is not false and not contradictory. The commenter doesn't understand the per-required knowledge to the review the page..
"bit-accurate" refers the the sizing issue of an "int" in "high level" langauges (usage clarified down the page). The problem is that C/C++ software programmers inherently know that an "int" keyword is 16 bits OR 32 bits OR 64 bits depending on there target >>HARDWARE<< platform.. BUT the coder of a behavioral synthesis system is writing the new >>HARDWARE<<. There is no convention yet set for these "int"s .. you must communicate this knowledge to the synthesis tool, hence "bit-accurate" libs(libs that are explicit about what the size of the varaibles are) are required so that the tool can determine what the coder means. This that "bit-accurate" lib written in C/C++ would replace usage of "int" with "int32_t" and so on...

"The code is analyzed, architecturally constrained, and scheduled to create synthesizable HDL"

Also strange phrase. When you synthesize your "high level" code, you create synthesizable HDL?

AGAIN The commenter doesn't understand the per-required knowledge to the review the page..
"high level languages" to refer to languages that are abstract in nature. This means a language which focus on the data manipulation rather then the how of the data manipulation (Eg C/C++ would be classifiable as "high-level" but not assembly). coding in a HDL language for hardware is like coding in a software assembly language, you directly specify the HOW of the data computation... EG you dont say give me "a + b". You pick a particular ALU design and code.. http://cseweb.ucsd.edu/classes/sp10/cse141L/pdf/02/02-Verilog2.pdf

Hi there, thanks. I tried to make the clarifications you suggested. Will check back. One comment I am still working on clarifying is the 'bit-accurate library', so I deleted it for now. Also working on filling in the additional citations over the next week. Mukis (talk) 08:45, 7 February 2009 (UTC)[reply]

Clarified the bit accurate class library in a separate section, with source cited. Still need 2 citations. Mukis (talk) 18:17, 7 February 2009 (UTC)[reply]

imparciality

This article is badly written, contains false information and publicity about vendors tools. It also cites only magazines, which is both not scientific nor trustworthy, as those magazines are paid by the CAD industry (no clear limits between publicity and real information).

WP:SOFIXIT; or give some sources here and I'll help. Or say what's spam and we can take it out. Dicklyon (talk) 23:03, 3 February 2009 (UTC)[reply]

Hi. I had read Wikipedia guidelines on references, then reviewed and other Wikipedia pages and thought reputable industry articles were fine (the particular The EETimes and SCD Source editor is well-known for doing independent research and an holding independent view) - but given your concern I am putting in another paper not from a publication, and will look for another relevant one over the next week. I will try to fill in the other citation requests. Thanks. Mukis (talk) 08:58, 7 February 2009 (UTC)[reply]

Hi again. I added in more two more requested source citations, this time from peer reviewed conference paper and university paper. Removed the 'unreliable source' comment with these last 2 changes. Please let me know on my talk page if you have other comments. Mukis (talk) 18:26, 29 March 2009 (UTC)[reply]

Hi - not sure if the unreliable source comment was from you or the impartiality comment, so posting this in both places. I added in more two more requested source citations, this time from peer reviewed conference paper and university paper. Removed the 'unreliable source' comment with these last 2 changes. Please let me know on my talk page if you have other comments. Mukis (talk) 18:27, 29 March 2009 (UTC)[reply]

Spam/coi?

Paul Chaffey, an application engineer for ChipVision, has been adding links to his company. I removed it once, but I'll leave it along for now and let others decide what to do about it. Dicklyon (talk) 23:55, 3 April 2009 (UTC)[reply]

C etc.

Don't Verilog and VHDL have their own behavioral sub-languages? The emphasis on C-type stuff seems a little odd here. Tijfo098 (talk) 20:39, 9 April 2011 (UTC)[reply]

Mmkay, from the VLSI handbook, 2nd ed., System-level design chapter, p. 76-4 (no typo): "Extensions of VHDL and Verilog have been proposed to encompass more system-level design properties. Apart from system constraints, VHDL specifications can form complete system descriptions. However, the level of detail required in VHDL and to some extent in Verilog requires the designer to make some implementation decisions. In addition, some information that is explicit in more abstract specifications such as the flow of control between tasks is implicit in HDLs." Someone may want to add a clarification to the article. Tijfo098 (talk) 20:45, 9 April 2011 (UTC)[reply]

Tagged it for bias. I don't know what the industry acceptance of these is, but there are just as many SystemVerilog books as there are for SystemC. See also [1] [2]. Tijfo098 (talk) 22:48, 9 April 2011 (UTC)[reply]

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