Talk:Costas loop

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Is the text from here? [1]--Light current 09:34, 21 October 2006 (UTC)

Clean up

It would be nice to refine or clean up the Costas loop Wikipedia page. While the filters for removing the high frequency components in the outer branch of the loop can be easily understood, the purpose of the third filter that links to the VCO is not explained. Also, the diagrams are all showing the Costas loop in the 'locked' state. But nobody shows how the Costas loop gets from unlocked state to the locked state. Also, formulas like $f^{1}{\big (}\theta ^{1}(t){\big )}^{2}$ are confusing, as it is unclear what $f^{1}$ and $\theta ^{1}(t)\$ actually means. And what does $\theta ^{1}(t)\$ mean? What is the meaning of those superscript '1's? The Costas loop Wikipedia page should include notes about unlocked state systems where the instantaneous phases (and frequencies) of the incoming signal and the VCO output signal are different to begin with. Also, the diagram having the caption "Costas loop before synchronization" needs to be fixed up, because it currently has a sin($\theta _{2}\$) expression coming out of the VCO, which doesn't make sense. And it also has an expression going into the VCO that doesn't make sense - because it appears that the expression is meant to go to zero - but if the input to the VCO goes to zero, then the VCO output would oscillate at its pre-configured free-running oscillation frequency, which clearly isn't right. If there is a difference in phase between incoming signal and the VCO (in the frequency-locked state - with a constant phase difference between the VCO and incoming signal), then one would expect that the VCO would eventually be supplied with a relatively constant voltage, since the the VCO input (proportional to SIN of twice the phase difference) is NOT meant to be zero. That is, the input to the VCO shouldn't become 'zero' at steady state (which is what those diagrams currently suggest). Also, a confusing piece of information that is currently (and misleadingly) presented toward the bottom of the Costas loop Wikipedia article page indicates that the classical Costas loop will make the VCO's phase equal to the incoming carrier's phase is just plain wrong. The math theory indicates that when the Costas loop is in the frequency-locked state, the signal going into the VCO will be equal to the SIN of {twice the difference in initial instantaneous phase} (between the carrier and the VCO). And, obviously, if indeed the misleading information (about carrier and VCO phase eventually becoming the 'same') is assumed to be correct (hypothetically), then the SIN of zero would be zero, which would imply that the input to the VCO would be ZERO in the locked state, which should NOT occur - because a zero input to the VCO means free-running oscillator mode. Obviously, the VCO is not meant to be free-running at steady-state. Also, the equation with the input to the VCO being the SIN of twice the phase difference should also have a multiplying factor of 1/8 [ie. (1/8)*SIN is missing in the diagram that is currently captioned with "Costas loop before synchronization"]. A particular Wiki user indicates in the 'history' section that classical Costas loop will make the phase difference equal by means of 'integration'. However, if that is what the user believes, then the user should add diagrams and extra math equations to demonstrate it. Otherwise, it just isn't helpful to contradict the math theory shown in the Costas loop Wikipedia page. — Preceding unsigned comment added by KorgBoy (talk • contribs) 12:06, 8 March 2017 (UTC)

Your comments about what the filter does are confused. You should consult some sources, but for a simple tweak consider that the DC gain of the filter is arbitrarily large. Consequently, even a tiny phase difference will produce a significant voltage to the VCO. That is the game that opamps play every day. Glrx (talk) 03:19, 11 March 2017 (UTC)

On the contrary. You're the one that is confused. The mathematics shown in the diagrams clearly show that the input to the VCO is proportional to the Sine of twice the phase difference between VCO and incoming sinusoid signal. The math from other sources indicate the same. Clearly, if the phases are identical, then sin of zero gives zero, which implies an input signal of zero to the VCO, which is obviously wrong. If you don't agree, then go ahead and add some extra diagrams. Or replace the math equations with ones that you think are 'correct'. See the diagram with the caption of "Costas loop before synchronization". That one. The input signal to the VCO clearly indicates SIN of twice phase difference, which pretty much aligns with the theory from other sources - except they forgot to put in a factor (1/8) next to the SIN(). Also, that diagram clearly does not show the SIN() signal being integrated. The diagram clearly shows a signal proportional to the SIN of twice phase difference driving the VCO. You should focus on that particular diagram I'm talking about. If that diagram is wrong, then please fix it up. KorgBoy (talk) 12:42, 11 March 2017 (UTC)

• "the diagrams clearly show that the input to the VCO is proportional to the Sine of a phase difference"
• "gives zero, which implies an input signal of zero to the VCO"
• "diagram clearly does not show the SIN() signal being integrated"

None of those statements need be / are true.

Nothing prevents the pre-VCO filter from having a transfer function with a pole at zero; such a pole allows a nonzero output for zero input; such an output is not proportional.

The article states "the phase difference between the carrier and the VCO become a small, ideally zero, value". The article does not state the difference must be zero. A phase difference of one degree can be "small" but still cause a significant change in VCO frequency.

Find reliable sources that support your claims.

Glrx (talk) 19:16, 11 March 2017 (UTC)

Firstly, please attempt to look at that particular diagram captioned "Costas loop before synchronization" and the math expression shown in that diagram describing the input signal to the VCO (which I pointed out). Otherwise, if you continue to ignore that diagram and equation, then it won't be helpful to the discussion. If you want to discuss the issue, then please focus on that particular diagram (and math expression for the VCO input). One source you should look at is : http://dsp-book.narod.ru/costas/DSP010315F1.pdf - which shows a diagram (Fig 3.) having an expression for the input signal going to the VCO. Now, even though the expression in Fig 3. has a factor of (1/4), it appears to be a minor typo. The factor should actually be (1/8), but that's ok since it's not going to change the picture very much. From that math expression, you can surely see that if the phase difference between VCO and incoming signal (at steady-state) were 'small' or even 'zero', then the input signal to the VCO would be zero, or close to zero - which is not wanted. This indicates that the actual phase difference at steady-state is likely to be some constant value that is not only non-zero, but is also not 'small' in general. And, getting back to your comment about 'integrating' that signal. It is not going to help make that steady-state phase difference become 'small' or zero. And, besides, the diagrams don't show that signal being 'integrated' in the first place. And even if you did integrate that signal, it is just going to upset the Costas loop control process, and end up with nothing working at all (ie. no frequency lock). Finally, your comment about "None of those statements need be / are true." essentially implies that the math expressions and diagrams currently shown in the Wikipedia Costas loop page are wrong. They're not wrong (once the mistakes are fixed that is). The only thing that is mainly wrong is the contradictory statement toward the bottom of the Wikipedia Costas loop page, that says the phase difference at steady-state will be zero, or close to zero. That comment contradicts the SIN(2 times phase difference) VCO input expression. You mention integrator. Please show the integrator. Where is it? Please update the diagram if you believe that an integrator can be inserted somewhere, and show how it will work. Finally, the diagram with the caption "Carrier and VCO signals after synchronization" provides a correct account of the situation. You can see in that diagram that the phase difference between carrier and VCO (when frequency lock is achieved) is certainly not zero, and is certainly not small. So, could you please remove the erroneous information that currently says "The classical Costas loop will work towards making the phase difference between the carrier and the VCO become a small, ideally zero, value. The small phase difference implies that frequency lock has been achieved.", and put back what I had originally added (prior to its removal)? KorgBoy (talk) 22:45, 11 March 2017 (UTC)

I've reverted you again. Please do not re-add without gaining consensus for your changes on this talk page. Yes, you've looked things over and believe you are right, but what you've done is original research, and that is not acceptable authority for Wikipedia. There's a lot going on, and you are not considering K_φ, K_VCO, and the possibilities of a PID controller. Gardner, in his book on the closely related PLL discusses third-order control loops that drive final value phase differences to zero. Glrx (talk) 20:48, 23 March 2017 (UTC)

I have reverted you because the diagram "Carrier and VCO signals after synchronization" clearly shows that the phase difference (after frequency lock has been established) is not small. Please look at it and be rational. Otherwise, you might as well remove that diagram too if you believe that you're correct. I recommend that you not revert my entries, unless you're prepared to remove that particular diagram "Carrier and VCO signals after synchronization" (which was introduced by somebody else). All the details on the Costas Loop Wikipedia page relate to the 'classical' Costas loop. If you are keen to create your own clear diagram of a non-classical Costas loop system that frequency-locks with zero phase difference (and justify how it works), then please do so. And, please do not add material that contradicts the diagram "Carrier and VCO signals after synchronization" and theory presented at the Costas Loop Wikipedia page. I recommend that you read the Wikipedia introductory information for the Costas Loop page. It begins with the title "Classical implementation". Pay particular attention to the sentence "the third low-pass filter serves a trivial role in terms of gain and phase margin". Also, what I told you isn't 'research'. What I told you is obvious. If you can show or demonstrate how third order filtering in this particular classical Costas loop setup is going to help you drive the phase difference to a very 'small' value, then we may having something to discuss here. You mention certain parameters haven't been 'considered'. Show us exactly what these considerations are. For example, your introduced idea of a 'pole at zero' (pure integrator). Explain how the integral of sin(2.theta) is going to help with anything. Show us your working model. If you can do (produce) that, then it will be a useful contribution. That is - don't 'consider'. Show. Show what you mean - clearly. Also note that the results from those plots from the figure "Carrier and VCO signals after synchronization" are reproducible. Also, keep in mind that this classical Costas Loop system is based on multipliers and basic low-pass filtering. If you try to tinker with this system and add your integrator (and so on), you'll end up with something that won't operate at all. The main reason for purposefully stating that the classical Costas loop system does not lock with a zero phase-difference is for clarity, and avoids confusion for cases where one might intuitively or instinctively (but yet mistakenly) assume that it locks with a zero (or even a 'very small') phase-difference. In fact, if the carrier and VCO signals are set to have the exact same frequency but with a phase difference (to begin with), the classical Costas loop will eventually settle and will frequency-lock with a 90 degree phase difference between carrier and VCO. Naturally, while the basic theory math equations are simple enough, the loop process is iterative, and the way that the system achieves frequency-lock with a constant phase difference (at steady-state) takes a little bit of thinking about the expression for the input signal to the VCO prior to reaching the frequency-locked state (ie. prior to steady-state). But, what happens in the wings is that the VCO frequency and carrier frequency eventually become equalised at steady-state (assuming free-running VCO frequency and incoming carrier frequency were initially different), which leaves a typically finite voltage at the VCO input (which is responsible for the equalised frequency), and that steady-state VCO input voltage will be proportional to the sine of the 'twice the phase difference between carrier and VCO'. That steady-state phase difference will generally be far from 'small'. Also, importantly, I fully respect your views. I was just trying to add particular points on the main page to clarify a few things. ( — Preceding unsigned comment added by KorgBoy (talk • contribs) 04:49, 24 March 2017 (UTC)

Yes, please revert your edit and remove the misleading diagram "Carrier and VCO signals after synchronization". If you look at the diagram "Costas loop after synchronization" it shows the carrier frequency as sin(ωt) and the VCO frequency as sin(ωt). Consequently, those two signals are (for practical purposes) in phase. The diagram "Carrier and VCO signals after synchronization" is plotting the input carrier and a -90° shifted VCO. Glrx (talk) 00:04, 26 March 2017 (UTC)

The plot is truly plotting carrier and VCO (not the -90 degrees VCO that you think). The figure title indicates 'VCO'. It does not indicate "-90 degrees VCO". As I had mentioned in my "Clean Up" comments, some math expressions in the figures have TYPOS (errors) in them. The schematic diagram "Costas loop after synchronization" has an expression at the output of the VCO that currently says sin(ωt). It is a 'typo'. It should actually be "sin(ωt+theta_d)", where theta_d is phase difference between carrier and VCO. Be wary about some of those math expressions in those schematics, as I had mentioned that some are wrong (re: my Cleanup comments). And, the main point is: the steady-state phase difference theta_d between carrier and VCO is generally far from small. It must not become 'small' or 'zero', otherwise the input to the VCO would become zero, resulting in a free-running VCO (which is not desired). And, due to constraints of the multipliers and low-pass filters, you cannot just go ahead with inserting integrators etc in hopes of making the phase difference go to zero. Sure, for other PLL systems involving early/late phase detector pulses etc, you could start thinking about pure integrators etc. But not in this case where the system is based on simple multiplication and low-pass filtering. The nice thing is that you notice some things that I notice, such as 'typos' in some of the math expressions in some figures. I didn't put those figures there. Somebody else did, and they weren't careful enough in making sure that their maths expressions were correctly added, which led to my 'Clean Up' comments. Note that the opening figure "Costas loop" should also have the VCO output as being sin(ωt+theta_d), but at the moment, it has only sin(ωt). The carrier and VCO cannot be in-phase at steady-state, otherwise the VCO's input signal would be zero (ie. not desired). I recommend taking a look at the notes at this link here : http://dsp-book.narod.ru/costas/DSP010315F1.pdf , where you will be able to see the error signal expression for VCO input (except, the '1/4' factor needs to be replaced with 1/8). There, they used cos and -sin for the quadrature VCO signals. No matter which way we look at it, the VCO input will be proportional to the SINE of twice the phase difference when frequency-lock is achieved. So, as you can see - a zero phase difference would make the VCO turn into a free-running VCO. And a free-running VCO is obviously not going to help achieve frequency lock. Therefore, the steady-state phase difference will be non-zero, and not small. No need for further discussion until you seriously read those notes and until you understand that VCO input being proportional to sin(2.theta_d) implies theta_d is not expected to be 'very small', otherwise a very small (or zero) VCO input would result in a free-running VCO. Tried to get this across to you many times already. KorgBoy (talk) 00:25, 26 March 2017 (UTC)

I've reverted you again.[2] Your additions were unsourced and represent your take on the Costas loop rather than a reliable source's. I've reluctantly put a WP:3RR warning on your talk page. Your edits are all good faith, but they need better foundation. You continue to make claims about a significant phase difference.

See Feign, http://mobiledevdesign.com/site-files/mobiledevdesign.com/files/archive/mobiledevdesign.com/images/archive/0102Feigin20.pdf , stating "Finally, the carrier must be recovered. Its frequency and phase needs to be exactly reproduced to optimally demodulate the BPSK signal." Exactly reproducing the phase implies the phase difference is small. That is the position that previous editors of this WP article have stated.

Feign also states, "The PLL is locked when the phase detector result is zero (near zero when the loop filter is not a true integrator), hence producing a DC constant at the input of the VCO." Integrators are used so a zero phase difference can produce the DC offset needed to tune the VCO.

Glrx (talk) 16:43, 27 March 2017 (UTC)

You obviously did not go through the well-presented material at http://dsp-book.narod.ru/costas/DSP010315F1.pdf - which is a good source for beginning to understanding Costas loop behaviour. Note - even when there is a constant phase difference when the frequencies are locked, a scaled version of the message signal m(t) will still appear at one (or either) of the outer filter outputs. The message will simply be scaled by either (1/2)$\sin(\theta _{d})$ or (1/2)$\cos(\theta _{d})$. Those scaling factors are clearly seen in equation (15) and (18) of Feigin's paper when the carrier frequency and VCO frequency equalises. Anyone that says the classical Costas loop system will frequency-lock with a very small or even zero phase-difference (between carrier and VCO) is mistaken. In http://mobiledevdesign.com/site-files/mobiledevdesign.com/files/archive/mobiledevdesign.com/images/archive/0102Feigin20.pdf you may have noticed that Feigin's paper does not show plots of carrier and VCO phase in the frequency-locked state (simulated or otherwise) being "in-phase". In fact, it does not show phase comparison plots at all. The only figure that I've seen that is on the 'right track' is the one in the figure "Carrier and VCO signals after synchronization" on the Wikipedia Costas loop page. Your reverting of the details that I added will leave readers confused due to various erroneous pieces of information 'initially' presented there. And, sometime in the future, you're going to have to put back what you deleted - when you eventually realise that all the details that I told you are accurate. Exercise your mathematical skills and rationality by investigating a few details that I told you about. A little bit of effort on your part would easily have allowed you to confirm details that I had added. If you want to show that you are seriously interested in this topic about Costas loop, then get in there and find out for yourself which details are accurate, and which are not. Use your mathematical ability to show for yourself that Costas loop will never lock with a very small (or even zero) phase difference between carrier and VCO. Feigin indeed wrote "Finally, the carrier must be recovered. Its frequency and phase needs to be exactly reproduced to optimally demodulate the BPSK signal.". Note that Feigin wrote 'to optimally demodulate'. Focus on the word 'optimally'. Feigin did not mention that the Costas loop will lock with a zero phase difference. If you mistakenly assume that Costas loop will lock with zero (or very small) phase difference, then you basically caught the wrong bus. Feigin's statement "The PLL is locked when the phase detector result is zero (near zero when the loop filter is not a true integrator), hence producing a DC constant at the input of the VCO." has issues. That particular sentence does not make sense because - first of all, one cannot just insert an integrator into the classical Costas loop system and expect the system to function properly. Although, I believe that Feigin is referring to the special case where carrier and free-running VCO are set up with the same initial frequency (to begin with). In that case, yes, the input to the VCO could become zero - but only for that special case. And such a special hypothetical case might not reflect practical situations, unless we use precise frequency standards at both the transmitter and receiver sides. KorgBoy (talk) 12:02, 28 March 2017 (UTC)

In, http://mobiledevdesign.com/site-files/mobiledevdesign.com/files/archive/mobiledevdesign.com/images/archive/0102Feigin20.pdf just before equation (2), Feigin also writes "The phase-detection response is described by Costas Phase Detector", which has issues, because it follows up with "This result is similar to that of a conventional multiplier-type phase detector". The issue here is that - a classical Costas Phase Detector is (itself) a conventional multiplier-type phase detector in the first place. So, you'll have to ask what Feigin was trying to write there. Now, very importantly - Feigin writes "The cosine response of the multiplier phase detector causes a lock when the phase error is 90° (because the cosine of 90° is zero)". I will point out to you that this is equivalent to sin of (2*90) = 0, which you had deleted (re: my Wikipedia addition), which also corresponds to the special case (that you deleted as well) where the initial carrier and free-running VCO signal are set (eg. by simulation) to be identical in phase and frequency to begin with. Let me ask you this - does locking with 90 degrees phase difference sound like a 'very small' phase difference? The answer is 'no'. For real (practical cases) where the carrier and VCO frequencies could be different to begin with, and where the initial instantaneous phases of carrier and VCO are arbitrary values, the Costas loop system will work towards equalising the frequencies, and it will finally arrive at a constant value for the steady-state phase difference (as I had mentioned, but you deleted that too from the Wikipedia Costas loop page). So what does this say about the statements that you keep putting up (yourself) at the bottom of the Costas loop Wikipedia page? Namely - "The classical Costas loop will work towards making the phase difference between the carrier and the VCO become a small, ideally zero, value. The small phase difference implies that frequency lock has been achieved.". Well, basically - it is erroneous information. My recommendation - remove it. And put back all the details I added in order to avoid confusing readers due to other errors and/or over-simplifications currently shown in the Costas loop Wikipedia page. Also, for the classical Costas loop, remember that I once indicated (on the Costas loop Wikipedia page, but you deleted it) that sin(2.theta_d) can have various solutions. For example, plugging theta_d = 2.29428287 degrees into the sin expression will give the same result as theta_d = 87.70571713 degrees, and theta_d = -92.29428287 degrees. So, whatever the steady-state phase difference will become at the end of the Costas loop iterative process, it should be possible to assess the phase difference value (by means of a phase difference "measurement") once frequency-lock has been achieved. KorgBoy (talk) 12:02, 28 March 2017 (UTC)

Glrx - I reverted you once more, due to your misleading comments about the author's definition of 'phase error' as meaning phase difference between carrier signal and 90-degrees-shifted VCO signal. That is not the author's definition at all. You conjured this, and it is wrong. The phase error (at steady-state) obviously means phase difference between carrier and *VCO* (not 90-degree-phase-shifted VCO). The comparison is done between carrier signal and the VCO's *immediate* output. Also, your addition about carrier and VCO phase difference being equal to zero (or approximately zero) at steady-state is nonsense. The behaviour of the classical Costas loop system is bound by the mathematics of the classical Costas loop scheme, which involves simple multiplier blocks and simple low-pass filtering. You don't appear to understand this, and you also don't appear to understand that the classical Costas loop scheme (with simple multiplier blocks and low-pass filtering) cannot accommodate components such as pure integrators. I won't be reverting you again, regardless of what you do on the Costas loop Wikipedia page. I will let somebody else sort you out in the future. KorgBoy (talk) 06:12, 1 April 2017 (UTC)

Look at this article's figure in the classical loop section; the VCO sin phase goes to the top multiplier and the VCO cos phase goes to the bottom multiplier. Notice also that center filter is a "loop filter" and not a "low pass filter" (LPF) as in the top and bottom paths. Loop filters are used to set feedback performance and may contain integrators (see PID). As stated above, integrators can produce a nonzero output with a zero input; an integrator will drive the steady state error to zero.

The Wikipedia article's figure "Costas loop after synchronization" is consistent: the un-phase-shifted VCO (sine) goes to the top multiplier and -90° shifted version (a cosine) goes to the bottom multiplier. The center filter is just labeled "Filter"; it is not explicitly called out as a loop filter. The WP article schematics are consistent.

Now look at Feigin's figure 7: unlike the WP schematics, the VCO output is phase shifted when it is sent to the top multiplier and is not phase shifted when it is sent to the lower multiplier. That's why Feigin has the phase difference between the carrier and the VCO being 90° while the Wikipedia article states it is zero. The VCO phase choice is arbitrary, but it should be consistent within one article. It is that arbitrary VCO phase choice that has "Carrier and VCO signals after synchronization" showing a 90° phase difference: that figure is for the other (Feigin's) choice of VCO phase rather than this article's choice. It is showing 90°; it is not showing a significant departure from 90°.

Glrx (talk) 21:10, 2 April 2017 (UTC)

You are wrong again Glrx. You don't understand the meaning of the '0 degree' symbol and the '90 degree' symbol in the phase shifter module. The '0 degree' symbol means 'VCO output', which is the immediate VCO output, or the output of the VCO itself. The '90 degree' symbol means 'The VCO output phase-shifted by 90 degrees', which is not the 'VCO output' at all. Note the words 'VCO output shifted by 90 degrees', or '90 degrees phase-shifted VCO'. Neither of these are the "VCO output". You also don't understand that the loop filter will be of a low-pass variety, for removing some noise (if any). Your idea of making the loop filter incorporate a pure integrator won't work. In fact, putting an integrator in the loop will make the system not function at all, ie. will not even frequency-lock. If you disagree, then would you (Glrx) like to show us all a working simulation model of the classical Costas loop system with your particular 'loop filter' (with your mentioned integrator) in the system? It would clear up everything entirely. And, you really do need to remove your erroneous information from the bottom of the Costas loop Wikipedia page, ie. the part that says "The classical Costas loop will work towards making the phase difference between the carrier and the VCO become a small, ideally zero, value. The small phase difference implies that frequency lock has been achieved.". It is a major mistake. Although, if you really believe that your major mistake is not a mistake, then please do show us your working simulation models. KorgBoy (talk) 07:21, 3 April 2017 (UTC)

Please look at Feigin figure 7 again. It differs from the diagram in the Wikipedia article, so its statements must adjusted when using them for comments about the Wikipedia article.

Roland E. Best, Phase-Locked Loops, third edition, McGraw-Hill, 1997, pp. 44–45. Among other things, Best states, "... the phase error θ_e is computed from the error transfer function H_e(s) as defined in Eq. (2.13). It turns out that the steady state error depends largely on the number of 'integrators' which are present in the control system, i.e., on the number of poles at s = 0 of the open-loop transfer function." Best uses the final value theorem to show the steady-state phase error for several conditions. Adding a single integrator to the loop filter (in addition to other poles and zeros of the loop filter) will drive the error to zero. Best states that adding more than one pole at zero to the loop filter is possible, but it complicates stability issues with little or no benefit.

A similar comment made by the Feigin source was given above. Floyd Gardner says the same thing, but I cannot find my copy of his book right now; IIRC, he calls it a third-order loop. Multiple reliable sources have no trouble using a loop filter transfer function with a pole at zero.

Glrx (talk) 17:31, 3 April 2017 (UTC)

No Glrx. You are wrong. Feigin's definition of phase error is the same as everybody else, except your own conjured distortion of it. Phase error is always phase difference between carrier and VCO (not "phase-shifted VCO"). Also, Roland E. Best's comments relate to particular forms of Phase Locked Loops that are able to accommodate (incorporate) loop filters that contain pure integrators. The classical Costas loop system, which is based on multiplier blocks (and low-pass filters for the outer branches) does not accommodate loop filters containing integrators. You should know that, because this control system doesn't involve the typical 'summer' or 'difference' block on the front end, unlike other phase locked loop systems that involve early/late pulses that will readily accommodate a pure integrator within the loop filter. If the classical Costas loop system is said to be based on simple multiplier blocks, and if the outer filters are low-pass filters for removing the high frequency components, then you're basically limited to using a low-pass filter (no pure integration) for the VCO branch. Somebody that understands basic control theory (such as you) should know that, right? If somebody (or some book or some paper or some Wikipedia page) says something that clearly doesn't add up, or is clearly wrong (such as usage of integrators within a classical Costas loop system based on multipliers and low-pass filters for the outer branches), it becomes necessary to indicate this and flag it. Don't catch the 'wrong bus'. First, apply what you've been taught (your mathematics and your control theory), and think about what you have been told (by me). I notice you have a tendency to avoid questions presented to you regarding showing (demonstrating) your ideas - such as when asked to go ahead with showing a working simulation of the classical Costas loop system with those pure integrators that you mentioned in the loop filter. Are you able to show a working simulation based on your comments about these integrators within the loop filter? I should also ask you - have you even seen a classical Costas loop system with an integrator at all - with full parameter details of the filter used? If so, then please immediately show it to us. My view - we do not see any diagrams in any book or any paper (or anywhere) that show classical Costas loop systems (based on multiplier blocks and low-pass filter outer blocks) featuring integrators, because it's just not going to work. Such a system you speak of is mythical. It would be nice if things worked as you want. But it doesn't in this case. People and students get confused about many teachings in text books and papers, because topics are not always properly explained, and certain pieces of information are over-simplified, or just plain wrong. Also interesting to encounter people like you that go around improperly policing the Costas loop page and removing additions from genuine contributors, and continuing to restore the erroneous details that you personally conjured. KorgBoy (talk) 18:56, 3 April 2017 (UTC)

Glrx. So, do you have any working simulations or diagrams of your classical Costas loop using integrators in the loop? I believe that you need to deal with the truth. You still need to remove your mistaken contribution from the Costas loop page, that currently (and wrongly) says "The classical Costas loop will work towards making the phase difference between the carrier and the VCO become a small, ideally zero, value. The small phase difference implies that frequency lock has been achieved.". You also need to realise that 'integrator loop filter' techniques go out the window when you have the multiplication blocks as entry points (instead of the general summer/differencer blocks from automatic control system theory). The classical Costas loop system works the way that it does due to the specific functional form of the input signal to the VCO, which is bound by the brilliantly conceived combination of the multiplication blocks and outer loop low pass filtering. Tinkering with the system by adding an integrator (and/or other incompatible components) is just going to render the loop unworkable - which boils down to not understanding what one is doing and blindly going ahead with it. I also recommend that you remove the irrelevant recent references that you added regarding integrators reducing phase error to zero. That theory doesn't apply to the classical Costas loop system. My view is that many articles, text books etc, are putting in misleading details that simply confuse people - because the details are erroneous or over-simplified to the point where the results are meaningless. KorgBoy (talk) 16:25, 13 April 2017 (UTC)

Glrx. Do not remove the figure that shows carrier signal and the VCO output after synchronisation. The figure is actually correct. I have Simulink simulations that fully support the results of that particular figure. I already explained to you that the Classical Costas loop will lock with a non-zero (and non-negligible) phase difference between carrier and VCO output. The catch is in details about the VCO input voltage is proportional to the sine of twice the phase difference. This knowledge is well-documented. Obviously, if the phase difference were zero (or even very small), then the VCO input voltage would become zero, which would represent an undesirable free-running VCO state. So this should tell you clearly that the Costas Loop is certainly not going to lock with zero phase difference under typical scenarios. Do not add or remove information that you have no understanding of. I can easily provide a Simulink model that simulates the locking based on that particular model shown in the article. If you have no model or idea about this subject, then please refrain from adding misleading information, and do not delete figures that are accurate. I also repeat (again) --- the following passage that you once added to the article (and is still there) is wrong - namely "The classical Costas loop will work towards making the phase difference between the carrier and the VCO become a small, ideally zero, value". It needs to be removed. KorgBoy (talk) 10:28, 20 August 2018 (UTC)

I've removed the figure again. The other figures in the section define the VCO phase as sin(). The carrier is sin(ωt) and the VCO is sin(ωt + θ_s). If, as you want, the phase difference were 90°, then θ_s = 90°. But that is disaster because then cos(θ_s)=cos(90°)=0 in the top branch of the Costas loop and therefore the branch's lowpass filter cannot recover m(t). See the first figure in the article where the top branch recovers the modulation. If the VCO has cosine phase, then the phase difference is 90°. Glrx (talk) 16:08, 21 August 2018 (UTC)

Don't remove that figure again Glrx. Otherwise I will certainly bring this to the attention of Wikipedia moderators. As I mentioned, I have Simulink models that supports that particular figure. If you insist that the figure is wrong, then go right ahead and provide a working Simulink model that gets your point across. I can certainly provide one that supports the figure. If you cannot, then do not meddle with the article by removing perfectly good figures - the hard work of that particular contributor. Your statement about 'disaster' is misplaced. The classical Costas loop can (and does) frequency-lock with a non-zero and non-negligible constant phase difference between carrier and VCO output signal. The phase difference at the frequency-lock condition can be whatever it pans out to be. The phase differences could be values like 2.29428287 degrees, or 87.70571713 degrees, or even -92.29428287 degrees. Notice how the sine of twice those mentioned angle values all turn out to be the same value. The resulting value will be a VCO input control voltage that makes up the difference between the carrier frequency and the initial free-running VCO frequency. This means that - at the frequency-lock condition, the phase difference will be constant, non-zero, and non-negligible. The reason you're deleting figures and adding erroneous information to the Costas Loop article is because you don't understand the topic very well (or at all). KorgBoy (talk) 19:50, 21 August 2018 (UTC)

Change of variables

I suggest to rename variables with upper subscript 1 and 2 to lower subscript {ref} and {vco}. This edit will make current article easier to read and understand. Marat Yuldashev 19:41, 8 August 2018 (UTC)