Talk:Compressed instruction set

A fact from Compressed instruction set appeared on Wikipedia's Main Page in the Did you know column on 11 May 2021 (check views). The text of the entry was as follows:

Did you know... that some microprocessors feature a compressed instruction set that packs machine-language instructions into a more memory-efficient size?

A record of the entry may be seen at Wikipedia:Recent additions/2021/May. The nomination discussion and review may be seen at Template:Did you know nominations/compressed instruction set.

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Did you know nomination

The following is an archived discussion of the DYK nomination of the article below. Please do not modify this page. Subsequent comments should be made on the appropriate discussion page (such as this nomination's talk page, the article's talk page or Wikipedia talk:Did you know), unless there is consensus to re-open the discussion at this page. No further edits should be made to this page.

The result was: promoted by Cwmhiraeth (talk) 06:22, 8 May 2021 (UTC)[reply]

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... that some microprocessors feature a compressed instruction set that pack machine language instructions into a more memory-efficient size? Source: SH-5 CPU Core, page 8

Reviewed: Glory to Rome

Created by Maury Markowitz (talk). Self-nominated at 22:35, 9 April 2021 (UTC).[reply]

The article is new enough and long enough with no copyright violations. A QPQ has been completed. The hook is fine, but the modern use section needs to be referenced. SL93 (talk) 21:57, 3 May 2021 (UTC)[reply]

@SL93: Added. Maury Markowitz (talk) 22:59, 3 May 2021 (UTC)[reply]

Thanks. This is ready. SL93 (talk) 23:19, 3 May 2021 (UTC)[reply]

Example involving 6502 shift instructions

I don't find the 6502 Logical Shift Left example entirely compelling. LSL only shifts one bit at a time, as anyone who has encountered 6502 assembly language will know, whereas the MIPS SLL instruction involves a shift of an indicated amount, and the MIPS SLLV instruction involves a shift indicated by another register value. If you have to shift multiple times on a 6502, you either have to replicate the instruction or introduce a loop, and the only practical mitigation is that many programs are likely to be manipulating 8-bit values and will therefore only perform four shifts in either direction to achieve a particular result. That might guarantee a code size reduction in all but one of the likely cases, but then again, that is comparing an 8-bit instruction on a processor operating on 8-bit values with a 32-bit instruction on a processor operating on 32-bit values, where programs written for the latter may well benefit from being able to perform shifts of greater magnitude. I think that comparable architectures to MIPS, such as the Motorola 68000 family or even the IBM 801, involving more directly comparable instructions, might provide a more compelling basis for such comparisons. PaulBoddie (talk) 21:13, 11 November 2024 (UTC)[reply]