Talk:Cache on a stick

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technical details?

The internet is sadly lacking on technical details for these old parts. In particular, what clock speeds do they run at, etc? I ask anyone who has such information, even if its an old IT manual, to improve this article.--ChrisJMoor 15:26, 30 July 2007 (UTC)[reply]

Well, L2 cache on those boards always ran at the FSB clock. So, a COAST module on a Socket 7 motherboard running at 66 MHz FSB would run at 66 MHz too. A COAST module can be seen as just a part of the mobo detached and stuck into a slot. By doing this they didn't lock a motherboard to a certain cache size and didn't have to worry about which mobo+cache size to manufacture in what quantity, say. The motherboard could run with any cache size. -- 20:26, 30 July 2007 (UTC)

Ahh, I see. Presumably its lower latency than the DRAM in the main memory... does not suggest much of a performance improvement really. If you know anything more or you can reference this, please add it. Just a personal story here - I was goofing around with my first ever PC trying to squeeze every last drop of performance from it (so it can stay useful as opposed to going to the dump) and the only stumbling block I encountered was this one item - I only knew of its existence, much less what types were available. I got one that worked when fitted but not after much hesitation for fear it would ruin my efforts So you see, some people actually still want to know this:D--ChrisJMoor 01:14, 31 July 2007 (UTC)[reply]

The latency difference is a bigger change than is intuitively evident. Let's say you have your 75MHz Pentium whirring happily away on a Socket 7 board with 80ns RAM. Ignore the effect of L1 cache (assume it was a cache miss) here. Processor goes to fetch data from RAM. 80ns RAM runs at 12.5MHz, so 6 processor cycles later, it can do what it originally wanted to. Now add some 12ns (83MHz) L2 cache to the equation. Assuming that the data you need is actually in L2 cache (a cache hit) it now gets the data in only one cycle. In other words, in a memory-bottlenecked situation (eg, read two numbers, add them together, write them out), you've gone from effectively having a 12.5MHz processor to being able to use the full 75MHz you paid for. (I pulled the above speeds from memory, but they should be approximately accurate.) Vykk (talk) 17:52, 14 May 2012 (UTC)[reply]

Incorrect

Apple Macintoshes did not use Cache DIMMs until the PowerPC era. They were used with most of the PPC601, 603, and 604 systems. 680X0 systems had cache that was either not upgradable, upgradable through a 120-pin Euro-DIN connector (IIci), through a '040 PDS (very rare) or through a 'slotless' module that plugged into the processor socket on the logic board, with the processor plugged back into the upgrade (also very rare). —Preceding unsigned comment added by 69.86.88.249 (talk) 05:15, 10 May 2010 (UTC)[reply]