Talk:CPU cache/Archive 2

Archive 1

Archive 2

VIPT Caches

The article says:

"Theoretically, VIPT requires more tags bits because some of the index bits could differ between the virtual and physical addresses (for example bit 12 and above for 4 KiB pages) and would have to be included both in the virtual index and in the physical tag. In practice this is not an issue because, in order to avoid coherency problems, VIPT caches are designed to have no such index bits (e.g., by limiting the total number of bits for the index and the block offset to 12 for 4 KiB pages); this limits the size of VIPT caches to the page size times the associativity of the cache."

There are many problems with the above paragraph.

0) "more tags bits" should be "more tag bits" 1) "more tag bits" -- more than what? To be clearer, the sentence should read "more tag bits than VIVT". And that would still only be true on architectures where the VA and PA were of identical size. This is not true of many CPUs or ISAs, where the VA is frequently 64bit but the PA is smaller, say 40bit e.g. the original AMD Opteron. 2) It is not true that "In practice this is not an issue because, in order to avoid coherency problems, VIPT caches are designed to have no such index bits" -- this is also exactly what the prior commenter Erlkoenig90 takes issue with. As s/he states, the "coherency problem" of synonyms can be solved if page-coloring is enforced in the OS. Page coloring is already covered elsewhere in the article, but it just needs to be mentioned that it also enables VIPT caches larger than (page size) * (cache associativity) -- by forcing the VA index bits that are common with the PA tag bits to always be identical. This coloring, in turn, forces synonyms to lie in the same cache set and way, avoiding incoherent duplicates that could otherwise exist in different cache sets at the same time. 3) Even with OSs that do not enforce page coloring, it is possible to have large VIPT caches. For example, the AMD Opteron processor and many other processors use VIPT Level 1 data caches whose (cache size) > (page size) * (cache associativity). They can do so precisely because they store ALL required bits of the physical tag, including any bits that "could differ between the virtual and physical addresses (for example bit 12 and above for 4 KiB pages)". As an example, the AMD Opteron has a 64KiB L1D cache that is 2-way set-associative. 64KiB > (4KiB * 2). The physical tag stores all address bits from bit 12 onwards. Bits 14:12 of the physical tag/address could differ from bits 14:12 of the virtual index/address. Microarchitectural mechanisms are employed to ensure that there are no coherency problems with synonyms. The cache management logic ensures that at any given time, there are no synonyms being duplicated in the cache.

If no one has objections, I can take a stab at updating the paragraph in question. — Preceding unsigned comment added by 73.202.190.91 (talk) 04:59, 13 March 2020 (UTC)

Cache flush

This article refers to the process of flushing the cache, but doesn't explain what that means. Also the page cache flush redirects to this page. So we should probably have a section explaining what it means to flush the cache. I.e. does it simply delete the cache data, or write the cache data to RAM, or both, or something else..?

JohnElliotV (talk) 07:28, 1 May 2020 (UTC)

Cache lines

CPUs, like Mips 10000 and intel CPUs, had a 128bit cache line size derived from 32bit memory bus and some dram to burst 4 data per access. Current Ram of course can burst an entire row of data. TaylorLeem (talk) 21:07, 11 October 2020 (UTC)

Conflict Miss Missing

The term "conflict miss" is used several times in the article, and is indicated as being defined somewhere inside it. The definition seems to be missing. I'd add one myself but, well, I came here to learn about caches and I don't know anything about them. I don't want to add incorrect info! Tsuyoshikentsu (talk) 01:02, 8 December 2020 (UTC)

Sentence fragment repeatedly added

@Oranjelo100: I reverted the sentence fragment Scratchpad memory has added by user:Oranjelo100 and he reinstated it. Worse, scratchpad memories aren't even relevant to caches. Shmuel (Seymour J.) Metz Username:Chatul (talk) 14:14, 22 February 2021 (UTC)