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5x misnomer

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Up to 5 times faster? Doubtfull: the multiple ALU and complex schedulers are power-expensive hardware -- so, how ARM could get 5x speedup? At least, reference needed.

According to this: http://www.bdti.com/InsideDSP/2010/10/19/arm -- dual core A15 will be 5x time faster than current single-core Cortex-A8, not Cortex-A9 MPCore. —Preceding unsigned comment added by 87.224.226.88 (talk) 18:14, 8 February 2011 (UTC)[reply]

15-stage out-of-order speculative issue superscalar execution pipeline, providing up to 5 times the performance of Cortex-A9 MPCore. ARM confirmed that the Cortex A15 core is 40 per cent faster than the Cortex A9 core, all things equal.

I'd like to get rid of the "up to 5 times" part, but thought it might be worth discussing because it isn't pure FUD. ARM actually has a graph where they divide up types of workloads on the chip compared to the A8 I think, and in the best workload segment it is something like 5 times better. Nvidia noted that their Kal El processor (Tegra 3) has been overclocked and fine tuned to the point that it is twice as fast as their Tegra 2 (both A9s), and that the graphics is 3 times faster, and has been pushing the "5 times better" mantra (such as in the famous logarithmic graph) for sound marketing reasons — but this is really a 2x + 3x = 5x, and not an outright 5 times faster performance.
I think this has an unfortunate resonance in the A9 to A15 comparisons, and many sources mistaken apply a "5 times better" label to a chip that is 40-50% faster, clock for clock, and also about 50% less in power. Still, if you assume that the 2Ghz design max for the A9 was overly optimistic (as no one has achieved it in practice) and compare a theoretical a15 @ 2.5Ghz to a run-of-the-mill A9 @ 1Ghz, the potential is maybe nearing 5x performance, definitely north of 2.5x performance which you can multiply out against the power savings to get a 5x performance over watts.
Anyone else agree that the "5-times the performance" blurp can go? It's a whole lot to take in if we were to go the other way and try to clarify where those numbers come from.
edit: after noticing all the above comments and repositioning my post with them, I'm going to take the plurality of similar opinions here as reason enough to go ahead proactively and remove the blurb. --— robbie page talk 18:51, 24 May 2011 (UTC)[reply]

how many bits?

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It would be nice if the specs listed whether this is a 32 or 64 bit CPU. —Preceding unsigned comment added by 95.209.23.48 (talk) 17:56, 26 April 2011 (UTC)[reply]

  • ARM is a 32 bit only processor architecture. You can have a 32 bit CPU that breaks the 4GB addressing barrier by adding extra address bits called PAE (physical address extension). Essentially the extra bits multiply the 4GB address space into multiple blocks of 4GB. The OS takes care of the rest. Intel started this with their Pentium Pro by adding 4 extra bits creating a 36 bit address bus. This allowed the OS to address upward of 64GB of memory, though Microsoft limited this to 4GB to desktop versions of Windows. Only certain 32bit server Operating systems from Microsoft were allowed to utilize PAE. Linux of course has no such restrictions and any user can take full advantage of PAE. 24.186.130.27 (talk) 15:08, 16 June 2011 (UTC)[reply]
Precise and good explaination. Thanks 24.186.130.27! :) 84.112.79.216 (talk) 15:06, 6 July 2011 (UTC)[reply]
ARMv8, announced 2011 October, is 64 bits. 24.186.130.27 could not have known the future four months ahead of time, but it is always unwise to say "ARM is only <anything too specific>". Fnj2 (talk) 21:08, 18 December 2011 (UTC)[reply]

LPAE

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The memory addressing is 40-bit, not 64-bit. You do need to go above 32-bit to get a full 1TB, but does that mean they actually implemented, and then gimped, a full 64-bit implementation? --— robbie page talk 18:09, 24 May 2011 (UTC)[reply]

  • If I recall correctly, they have some extra room left in their new page table format to grow the physical address. You'll have to register on ARM's site to get the docs for the details, though. I can understand why they might stop at 40 bits, though. Cache tags for a physically indexed cache would be over twice the size with 64-bit physical addresses vs. 40-bit physical addresses, so somehow I doubt they implemented a 64-bit design and hobbled it. Heck, even AMD's x86-64 extensions stopped at 48 bits of physical address. --Mr z (talk) 15:51, 17 November 2011 (UTC)[reply]

Requesting input

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The popularity of the Cortex M0 and M4 are starting to take off, thus it would be easier to pick some direction before having a bunch of tiny articles. Should there be unique articles for each of the ARM Cortex families? Should there be only 3 major ARM Cortex articles instead, and redirect all sub-flavors to these 3 new articles? Requesting input at Talk:List of ARM microprocessor cores#Discusion for ARM Cortex article overhaul for comments! • Sbmeirow • Talk • 17:14, 5 December 2011 (UTC)[reply]

ARM Cortex-A15 lacks an integer hardware division instruction

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Does anyone have evidence that any Cortex-A15 chips have an integer hardware division instruction? The GNU compiler isn't proof of what is inside of the silicon.

• Sbmeirow • Talk • 14:26, 11 January 2012 (UTC)[reply]

Slide 9 here indicates that the processor supports an integer divide instruction (and slide 27 indicates that it is implemented in the multiply/divide execution cluster). Jakew (talk) 14:48, 11 January 2012 (UTC)[reply]

It's now a moot point anyway, as the referenced page was edited to mention some new ARM processors do support division in hardware. ZPedro (talk) 22:10, 12 December 2012 (UTC)[reply]

Samsung Chromebook & Exynos5250

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I think the Exynos will be available soon. Google/Samsung wouldn't announce their Chromebook if it takes half a year before shipment. — Preceding unsigned comment added by 84.106.240.13 (talk) 10:09, 19 October 2012 (UTC)[reply]

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