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SYCL

From Wikipedia, the free encyclopedia
Not to be confused with Cilk.
SYCL
Original author(s)Khronos Group
Developer(s)Khronos Group
Initial releaseMarch 2014; 10 years ago (2014-03)
Stable release
2020 revision 8 (1.2.1) / 19 October 2023; 12 months ago (2023-10-19)[1]
Operating systemCross-platform
PlatformCross-platform
TypeHigh-level programming language
Websitewww.khronos.org/sycl/ sycl.tech

SYCL (pronounced "sickle") is a higher-level programming model to improve programming productivity on various hardware accelerators. It is a single-source embedded domain-specific language (eDSL) based on pure C++17. It is a standard developed by Khronos Group, announced in March 2014.

Origin of the name

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SYCL (pronounced ‘sickle’) originally stood for SYstem-wide Compute Language,[2] but since 2020 SYCL developers have stated that SYCL is a name and have made clear that it is no longer an acronym and contains no reference to OpenCL.[3]

Purpose

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SYCL is a royalty-free, cross-platform abstraction layer that builds on the underlying concepts, portability and efficiency inspired by OpenCL that enables code for heterogeneous processors to be written in a “single-source” style using completely standard C++. SYCL enables single-source development where C++ template functions can contain both host and device code to construct complex algorithms that use hardware accelerators, and then re-use them throughout their source code on different types of data.

While the SYCL standard started as the higher-level programming model sub-group of the OpenCL working group and was originally developed for use with OpenCL and SPIR, SYCL is a Khronos Group workgroup independent from the OpenCL working group since September 20, 2019 and starting with SYCL 2020, SYCL has been generalized as a more general heterogeneous framework able to target other systems. This is now possible with the concept of a generic backend to target any acceleration API while enabling full interoperability with the target API, like using existing native libraries to reach the maximum performance along with simplifying the programming effort. For example, the Open SYCL implementation targets ROCm and CUDA via AMD's cross-vendor HIP.

Versions

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SYCL was introduced at GDC in March 2014 with provisional version 1.2,[4] then the SYCL 1.2 final version was introduced at IWOCL 2015 in May 2015.[5]

The latest version for the previous SYCL 1.2.1 series is SYCL 1.2.1 revision 7 which was published on April 27, 2020 (the first version was published on December 6, 2017[6]).

SYCL 2.2 provisional was introduced at IWOCL 2016 in May 2016[7] targeting C++14 and OpenCL 2.2. But the SYCL committee preferred not to finalize this version and to move towards a more flexible SYCL specification to address the increasing diversity of current hardware accelerators, including artificial intelligence engines, which led to SYCL 2020.

The latest version is SYCL 2020 revision 6 which was published on November 13, 2022, an evolution from first release of revision 2 which was published on February 9, 2021,[8] taking into account the feedback from users and implementors on the SYCL 2020 Provisional Specification revision 1 published on June 30, 2020.[9] C++17 and OpenCL 3.0 support are main targets of this release. Unified shared memory (USM) is one main feature for GPUs with OpenCL and CUDA support.

At IWOCL 2021 a roadmap was presented. DPC++, ComputeCpp, Open SYCL, triSYCL and neoSYCL are the main implementations of SYCL. Next Target in development is support of C++20 in future SYCL 202x.[10]

Implementations

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  • Data Parallel C++ (DPC++): an open source project of Intel to introduce SYCL for LLVM and oneAPI. C++17 and parts of C++20 with SYCL 2020 are base of this compiler framework.[11][12]
  • ComputeCpp: SYCL 1.2.1 conformant framework of firm Codeplay with community version.[13][14] Now deprecated in favor of DPC++.[15]
  • AdaptiveCpp (formerly hipSYCL and Open SYCL): incomplete 1.2.1 support without Images or OpenCL interop; partly SYCL 2020.[16] Supports AMD (ROCm), Nvidia (CUDA), Intel (Level Zero via SPIR-V), and CPUs (LLVM + OpenMP).[17] Can produce fully generic binaries using a just-in-time runtime. Supports C++ standard parallelism (std::execution) in addition to SYCL.[18]
  • triSYCL: based on C++20, OpenMP and OpenCL, slow development, incomplete, with a version based on top of DPC++[19]
  • neoSYCL: SYCL 1.2.1 nearly complete, for hpc SX-Aurora Tsubasa, no OpenCL specific features like image support[20][21]
  • SYCL-gtx: C++11 support, for OpenCL 1.2+, far from complete, no actual development[22]
  • Sylkan is an implementation of SYCL to Vulkan devices in an experimental state.[23]
  • Polygeist has a fork compiling SYCL through MLIR[24] which is backed by the Inteon company.[25]

Extensions

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SYCL safety critical

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In March 2023 the Khronos Group announced the creation of the SYCL SC Working Group,[26] with the objective of creating a high-level heterogeneous computing framework for safety-critical systems. These systems span various fields, including avionics, automotive, industrial, and medical sectors.

The SYCL Safety Critical framework will comply with several industry standards to ensure its reliability and safety. These standards include MISRA C++ 202X,[27] which provides guidelines for the use of C++ in critical systems, RTCA DO-178C / EASA ED-12C,[28] which are standards for software considerations in airborne systems and equipment certification, ISO 26262/21448,[29] which pertains to the functional safety of road vehicles, IEC 61508, which covers the functional safety of electrical/electronic/programmable electronic safety-related systems, and IEC 62304, which relates to the lifecycle requirements for medical device software.[26]

Software

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Some notable software fields that make use of SYCL include the following (with examples):

  • Bioinformatics
    • GROMACS: A molecular dynamics software widely used in bioinformatics and computational chemistry. Starting from its accelerated version in 2021, GROMACS utilizes SYCL 2020 for efficient computation on various hardware accelerators.[30]
    • LiGen: A molecular docking software that utilizes SYCL for accelerating computational tasks related to molecular structure analysis and docking simulations.[31]
    • Autodock: Another molecular docking software that leverages SYCL to accelerate the process of predicting how small molecules bind to a receptor of a known 3D structure.[32]
  • Artificial Intelligence
  • Automotive Industry
    • ISO 26262: The international standard for functional safety of automotive electrical and electronic systems. SYCL is used in automotive applications to accelerate safety-critical computations and simulations, ensuring compliance with stringent safety standards.[34]
  • Cosmology
    • CRK-HACC: A cosmological n-body simulation code that has been ported to SYCL. It uses SYCL to accelerate calculations related to large-scale structure formation and dynamics in the universe.[35]

Resources

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Khronos Maintains a list of SYCL resource.[36] Codeplay Software also provides tutorials on the website sycl.tech along with other information and news on the SYCL ecosystem.

License

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The source files for building the specification, such as Makefiles and some scripts, the SYCL headers and the SYCL code samples are under the Apache 2.0 license.[37]

Comparison with other Tools

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The open standards SYCL and OpenCL are similar to the programming models of the proprietary stack CUDA from Nvidia and HIP from the open-source stack ROCm, supported by AMD.[38]

In the Khronos Group realm, OpenCL and Vulkan are the low-level non-single source APIs, providing fine-grained control over hardware resources and operations. OpenCL is widely used for parallel programming across various hardware types, while Vulkan primarily focuses on high-performance graphics and computing tasks.[39]

SYCL, on the other hand, is the high-level single-source C++ embedded domain-specific language (eDSL). It enables developers to write code for heterogeneous computing systems, including CPUs, GPUs, and other accelerators, using a single-source approach. This means that both host and device code can be written in the same C++ source file.[40]

CUDA

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By comparison, the single-source C++ embedded domain-specific language version of CUDA, which is named "CUDA Runtime API," is somewhat similar to SYCL. In fact, Intel released a tool called SYCLOMATIC that automatically translated code from CUDA to SYCL.[41] However, there is a less known non-single-source version of CUDA, which is called "CUDA Driver API," similar to OpenCL, and used, for example, by the CUDA Runtime API implementation itself.[38]

SYCL extends the C++ AMP features, relieving the programmer from explicitly transferring data between the host and devices by using buffers and accessors. This is in contrast to CUDA (prior to the introduction of Unified Memory in CUDA 6), where explicit data transfers were required. Starting with SYCL 2020, it is also possible to use Unified Shared Memory (USM) to augment, rather than replace, the buffer-based interfaces,[42] providing a lower-level programming model similar to Unified Memory in CUDA.[43]

SYCL is higher-level than C++ AMP and CUDA since you do not need to build an explicit dependency graph between all the kernels, and it provides you with automatic asynchronous scheduling of the kernels with communication and computation overlap. This is all done by using the concept of accessors without requiring any compiler support.[44]

Unlike C++ AMP and CUDA, SYCL is a pure C++ eDSL without any C++ extension. This allows for a basic CPU implementation that relies on pure runtime without any specific compiler.[40]

Both DPC++[45] and AdaptiveCpp[46] compilers provide a backend to NVIDIA GPUs, similar to how CUDA does. This allows SYCL code to be compiled and run on NVIDIA hardware, allowing developers to leverage SYCL's high-level abstractions on CUDA-capable GPUs.[45][46]

ROCm HIP

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ROCm HIP targets Nvidia GPU, AMD GPU, and x86 CPU. HIP is a lower-level API that closely resembles CUDA's APIs.[47] For example, AMD released a tool called HIPIFY that can automatically translate CUDA code to HIP.[48] Therefore, many of the points mentioned in the comparison between CUDA and SYCL also apply to the comparison between HIP and SYCL.[49]

ROCm HIP has some similarities to SYCL in the sense that it can target various vendors (AMD and Nvidia) and accelerator types (GPU and CPU).[50] However, SYCL can target a broader range of accelerators and vendors. SYCL supports multiple types of accelerators simultaneously within a single application through the concept of backends. Additionally, SYCL is written in pure C++, whereas HIP, like CUDA, uses some language extensions. These extensions prevent HIP from being compiled with a standard C++ compiler.[49]

Both DPC++[45] and AdaptiveCpp[46] compilers provide backends for NVIDIA and AMD GPUs, similar to how HIP does. This enables SYCL code to be compiled and executed on hardware from these vendors, offering developers the flexibility to leverage SYCL's high-level abstractions across a diverse range of devices and platforms.[46][45]

Kokkos

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SYCL has many similarities to the Kokkos programming model,[51] including the use of opaque multi-dimensional array objects (SYCL buffers and Kokkos arrays), multi-dimensional ranges for parallel execution, and reductions (added in SYCL 2020).[52] Numerous features in SYCL 2020 were added in response to feedback from the Kokkos community.

SYCL focuses more on heterogeneous systems; thanks to its integration with OpenCL, it can be adopted on a wide range of devices. Kokkos, on the other hand, targets most of the HPC platforms,[53] thus it is more HPC-oriented for performance.

As of 2024, the Kokkos team is developing a SYCL backend,[54] which enables Kokkos to target Intel hardware in addition to the platforms it already supports. This development broadens the applicability of Kokkos and allows for greater flexibility in leveraging different hardware architectures within HPC applications.[51]

Raja

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Raja[55][56] is a library of C++ software abstractions to enable the architecture and programming portability of HPC applications.

Like SYCL, it provides portable code across heterogeneous platforms. However, unlike SYCL, Raja introduces an abstraction layer over other programming models like CUDA, HIP, OpenMP, and others. This allows developers to write their code once and run it on various backends without modifying the core logic. Raja is maintained and developed at Lawrence Livermore National Laboratory (LLNL), whereas SYCL is an open standard maintained by the community.[39]

Similar to Kokkos, Raja is more tailored for HPC use cases, focusing on performance and scalability in high-performance computing environments. In contrast, SYCL supports a broader range of devices, making it more versatile for different types of applications beyond just HPC.[56]

As of 2024, the Raja team is developing a SYCL backend,[57] which will enable Raja to also target Intel hardware. This development will enhance Raja's portability and flexibility, allowing it to leverage SYCL's capabilities and expand its applicability across a wider array of hardware platforms.[39]

OpenMP

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OpenMP targets computational offloading to external accelerators,[58] primarily focusing on multi-core architectures and GPUs. SYCL, on the other hand, is oriented towards a broader range of devices due to its integration with OpenCL, which enables support for various types of hardware accelerators.[59]

OpenMP uses a pragma-based approach, where the programmer annotates the code with directives, and the compiler handles the complexity of parallel execution and memory management. This high-level abstraction makes it easier for developers to parallelize their applications without dealing with the intricate details of memory transfers and synchronization.[60]

Both OpenMP and SYCL support C++ and are standardized. OpenMP is standardized by the OpenMP Architecture Review Board (ARB), while SYCL is standardized by the Khronos Group.[39]

OpenMP has wide support from various compilers, like GCC and Clang.[61]

std::par

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std::par is part of the C++17 standard[62] and is designed to facilitate the parallel execution of standard algorithms on C++ standard containers. It provides a standard way to take advantage of external accelerators by allowing developers to specify an execution policy for parallel operations, such as std::for_each, std::transform, and std::reduce. This enables efficient use of multi-core processors and other parallel hardware without requiring significant changes to the code.[63]

SYCL can be used as a backend for std::par, enabling the execution of standard algorithms on a wide range of external accelerators, including GPUs from Intel, AMD, and NVIDIA, as well as other types of accelerators.[64] By leveraging SYCL's capabilities, developers can write standard C++ code that seamlessly executes on heterogeneous computing environments. This integration allows for greater flexibility and performance optimization across different hardware platforms.[64]

The use of SYCL as a backend for std::par is compiler-dependent, meaning it requires a compiler that supports both SYCL and the parallel execution policies introduced in C++17.[64] Examples of such compilers include DPC++ and other SYCL-compliant compilers. With these compilers, developers can take advantage of SYCL's abstractions for memory management and parallel execution while still using the familiar C++ standard algorithms and execution policies.[45]

See also

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References

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  1. ^ "Khronos SYCL Registry - the Khronos Group Inc".
  2. ^ Keryell, Ronan (17 November 2019). "SYCL: A Single-Source C++ Standard for Heterogeneous Computing" (PDF). Khronos.org. Retrieved 26 September 2023.
  3. ^ Keryell, Ronan. "Meaning of SYCL". GitHub. Retrieved 5 February 2021.
  4. ^ Khronos Group (19 March 2014). "Khronos Releases SYCL 1.2 Provisional Specification". Khronos. Retrieved 20 August 2017.
  5. ^ Khronos Group (11 May 2015). "Khronos Releases SYCL 1.2 Final Specification". Khronos. Retrieved 20 August 2017.
  6. ^ Khronos Group (6 December 2017). "The Khronos Group Releases Finalized SYCL 1.2.1". Khronos. Retrieved 12 December 2017.
  7. ^ Khronos Group (18 April 2016). "Khronos Releases OpenCL 2.2 Provisional Specification with OpenCL C++ Kernel Language". Khronos. Retrieved 18 September 2017.
  8. ^ Khronos Group (9 February 2021). "Khronos Releases SYCL 2020 Specification". Khronos. Retrieved 22 February 2021.
  9. ^ Khronos Group (30 June 2020). "Khronos Steps Towards Widespread Deployment of SYCL with Release of SYCL 2020 Provisional Specification". Khronos. Retrieved 4 December 2020.
  10. ^ https://www.iwocl.org/wp-content/uploads/k04-iwocl-syclcon-2021-wong-slides.pdf [bare URL PDF]
  11. ^ https://www.iwocl.org/wp-content/uploads/k01-iwocl-syclcon-2021-reinders-slides.pdf [bare URL PDF]
  12. ^ "Compile Cross-Architecture: Intel® oneAPI DPC++/C++ Compiler".
  13. ^ "Home - ComputeCpp CE - Products - Codeplay Developer".
  14. ^ "Guides - ComputeCpp CE - Products - Codeplay Developer".
  15. ^ "The Future of ComputeCpp". www.codeplay.com. Retrieved 2023-12-09.
  16. ^ "AdaptiveCpp feature support". GitHub. 4 July 2023.
  17. ^ "AdaptiveCpp/doc/compilation.md at develop · AdaptiveCpp/AdaptiveCpp". GitHub.
  18. ^ "AdaptiveCpp (formerly known as hipSYCL / Open SYCL)". GitHub. 4 July 2023.
  19. ^ "triSYCL". GitHub. 6 January 2022.
  20. ^ Ke, Yinan; Agung, Mulya; Takizawa, Hiroyuki (2021). "NeoSYCL: A SYCL implementation for SX-Aurora TSUBASA". The International Conference on High Performance Computing in Asia-Pacific Region. pp. 50–57. doi:10.1145/3432261.3432268. ISBN 9781450388429. S2CID 231597238.
  21. ^ Ke, Yinan; Agung, Mulya; Takizawa, Hiroyuki (2021). "NeoSYCL: A SYCL implementation for SX-Aurora TSUBASA". The International Conference on High Performance Computing in Asia-Pacific Region. pp. 50–57. doi:10.1145/3432261.3432268. ISBN 9781450388429. S2CID 231597238.
  22. ^ "Sycl-GTX". GitHub. 10 April 2021.
  23. ^ https://www.iwocl.org/wp-content/uploads/14-iwocl-syclcon-2021-thoman-slides.pdf [bare URL PDF]
  24. ^ "Polygeist". GitHub. 25 February 2022.
  25. ^ "Inteon". 25 February 2022.
  26. ^ a b "Khronos to Create SYCL SC Open Standard for Safety-Critical C++ Based Heterogeneous Compute". The Khronos Group. 2023-03-15. Retrieved 2024-07-10.
  27. ^ "MISRA". Retrieved 2024-07-11.
  28. ^ "ED-12C Aviation Software Standards Training - Airborne". Eurocae. Retrieved 2024-07-11.
  29. ^ "SOTIF – practical training". www.kuglermaag.com. Retrieved 2024-07-11.
  30. ^ https://www.iwocl.org/wp-content/uploads/k03-iwocl-syclcon-2021-trevett-updated.mp4.pdf [bare URL PDF]
  31. ^ Crisci, Luigi; Salimi Beni, Majid; Cosenza, Biagio; Scipione, Nicolò; Gadioli, Davide; Vitali, Emanuele; Palermo, Gianluca; Beccari, Andrea (2022-05-10). "Towards a Portable Drug Discovery Pipeline with SYCL 2020". International Workshop on OpenCL. IWOCL '22. New York, NY, USA: Association for Computing Machinery. pp. 1–2. doi:10.1145/3529538.3529688. ISBN 978-1-4503-9658-5.
  32. ^ Solis-Vasquez, Leonardo; Mascarenhas, Edward; Koch, Andreas (2023-04-18). "Experiences Migrating CUDA to SYCL: A Molecular Docking Case Study". International Workshop on OpenCL. IWOCL '23. New York, NY, USA: Association for Computing Machinery. pp. 1–11. doi:10.1145/3585341.3585372. ISBN 979-8-4007-0745-2.
  33. ^ "Llama.CPP/Docs/Backend/SYCL.md at master · ggerganov/Llama.CPP". GitHub.
  34. ^ https://www.iwocl.org/wp-content/uploads/20-iwocl-syclcon-2021-rudkin-slides.pdf [bare URL PDF]
  35. ^ Rangel, Esteban Miguel; Pennycook, Simon John; Pope, Adrian; Frontiere, Nicholas; Ma, Zhiqiang; Madananth, Varsha (2023-11-12). "A Performance-Portable SYCL Implementation of CRK-HACC for Exascale". Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis. SC-W '23. New York, NY, USA: Association for Computing Machinery. pp. 1114–1125. arXiv:2310.16122. doi:10.1145/3624062.3624187. ISBN 979-8-4007-0785-8.
  36. ^ "SYCL Resources". khronos.org. Khronos group. 20 January 2014.
  37. ^ "SYCL Open Source Specification". GitHub. 10 January 2022.
  38. ^ a b Breyer, Marcel; Van Craen, Alexander; Pflüger, Dirk (2022-05-10). "A Comparison of SYCL, OpenCL, CUDA, and OpenMP for Massively Parallel Support Vector Machine Classification on Multi-Vendor Hardware". International Workshop on OpenCL. IWOCL '22. New York, NY, USA: Association for Computing Machinery. pp. 1–12. doi:10.1145/3529538.3529980. ISBN 978-1-4503-9658-5.
  39. ^ a b c d "SYCL - C++ Single-source Heterogeneous Programming for Acceleration Offload". The Khronos Group. 2014-01-20. Retrieved 2024-07-12.
  40. ^ a b "SYCL™ 2020 Specification (revision 8)". registry.khronos.org. Retrieved 2024-07-12.
  41. ^ oneapi-src/SYCLomatic, oneAPI-SRC, 2024-07-11, retrieved 2024-07-11
  42. ^ "SYCL™ 2020 Specification (revision 9), 4.8. Unified shared memory (USM)". Retrieved 2024-10-30.
  43. ^ Chen, Jolly; Dessole, Monica; Varbanescu, Ana Lucia (2024-01-24), Lessons Learned Migrating CUDA to SYCL: A HEP Case Study with ROOT RDataFrame, arXiv:2401.13310
  44. ^ "Buffer Accessor Modes". Intel. Retrieved 2024-07-11.
  45. ^ a b c d e "DPC++ Documentation — oneAPI DPC++ Compiler documentation". intel.github.io. Retrieved 2024-07-11.
  46. ^ a b c d "AdaptiveCpp/doc/sycl-ecosystem.md at develop · AdaptiveCpp/AdaptiveCpp". GitHub. Retrieved 2024-07-11.
  47. ^ ROCm/HIP, AMD ROCm™ Software, 2024-07-11, retrieved 2024-07-11
  48. ^ "HIPIFY/README.md at amd-staging · ROCm/HIPIFY". GitHub. Retrieved 2024-07-11.
  49. ^ a b Jin, Zheming; Vetter, Jeffrey S. (November 2022). "Evaluating Nonuniform Reduction in HIP and SYCL on GPUs". 2022 IEEE/ACM 8th International Workshop on Data Analysis and Reduction for Big Scientific Data (DRBSD). IEEE. pp. 37–43. doi:10.1109/DRBSD56682.2022.00010. ISBN 978-1-6654-6337-9. OSTI 1996715.
  50. ^ Reguly, Istvan Z. (2023-11-12). "Evaluating the performance portability of SYCL across CPUs and GPUs on bandwidth-bound applications". Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis. SC-W '23. New York, NY, USA: Association for Computing Machinery. pp. 1038–1047. arXiv:2309.10075. doi:10.1145/3624062.3624180. ISBN 979-8-4007-0785-8.
  51. ^ a b Hammond, Jeff R.; Kinsner, Michael; Brodman, James (2019). "A comparative analysis of Kokkos and SYCL as heterogeneous, parallel programming models for C++ applications". Proceedings of the International Workshop on OpenCL. pp. 1–2. doi:10.1145/3318170.3318193. ISBN 9781450362306. S2CID 195777149.
  52. ^ Dufek, Amanda S.; Gayatri, Rahulkumar; Mehta, Neil; Doerfler, Douglas; Cook, Brandon; Ghadar, Yasaman; DeTar, Carleton (November 2021). "Case Study of Using Kokkos and SYCL as Performance-Portable Frameworks for Milc-Dslash Benchmark on NVIDIA, AMD and Intel GPUs". 2021 International Workshop on Performance, Portability and Productivity in HPC (P3HPC). IEEE. pp. 57–67. doi:10.1109/P3HPC54578.2021.00009. ISBN 978-1-6654-2439-4.
  53. ^ Trott, Christian R.; Lebrun-Grandié, Damien; Arndt, Daniel; Ciesko, Jan; Dang, Vinh; Ellingwood, Nathan; Gayatri, Rahulkumar; Harvey, Evan; Hollman, Daisy S. (2022), Kokkos 3: Programming Model Extensions for the Exascale Era, retrieved 2024-07-10
  54. ^ Arndt, Daniel; Lebrun-Grandie, Damien; Trott, Christian (2024-04-08). "Experiences with implementing Kokkos' SYCL backend". Proceedings of the 12th International Workshop on OpenCL and SYCL. IWOCL '24. New York, NY, USA: Association for Computing Machinery. pp. 1–11. doi:10.1145/3648115.3648118. ISBN 979-8-4007-1790-1. OSTI 2336667.
  55. ^ LLNL/RAJA, Lawrence Livermore National Laboratory, 2024-07-08, retrieved 2024-07-10
  56. ^ a b Beckingsale, David A.; Scogland, Thomas RW; Burmark, Jason; Hornung, Rich; Jones, Holger; Killian, William; Kunen, Adam J.; Pearce, Olga; Robinson, Peter; Ryujin, Brian S. (November 2019). "RAJA: Portable Performance for Large-Scale Scientific Applications". 2019 IEEE/ACM International Workshop on Performance, Portability and Productivity in HPC (P3HPC). IEEE. pp. 71–81. doi:10.1109/P3HPC49587.2019.00012. ISBN 978-1-7281-6003-0. OSTI 1488819.
  57. ^ Homerding, Brian; Vargas, Arturo; Scogland, Tom; Chen, Robert; Davis, Mike; Hornung, Rich (2024-04-08). "Enabling RAJA on Intel GPUs with SYCL". Proceedings of the 12th International Workshop on OpenCL and SYCL. IWOCL '24. New York, NY, USA: Association for Computing Machinery. pp. 1–10. doi:10.1145/3648115.3648131. ISBN 979-8-4007-1790-1.
  58. ^ tim.lewis. "Home". OpenMP. Retrieved 2024-07-10.
  59. ^ "OpenCL - The Open Standard for Parallel Programming of Heterogeneous Systems". The Khronos Group. 2013-07-21. Retrieved 2024-07-12.
  60. ^ Friedman, Richard. "Reference Guides". OpenMP. Retrieved 2024-07-12.
  61. ^ "OpenMP Compilers & Tools".
  62. ^ "std::execution::seq, std::execution::par, std::execution::par_unseq, std::execution::unseq - cppreference.com". en.cppreference.com. Retrieved 2024-07-10.
  63. ^ "Accelerating Standard C++ with GPUs Using stdpar". NVIDIA Technical Blog. 2020-08-04. Retrieved 2024-07-10.
  64. ^ a b c Alpay, Aksel; Heuveline, Vincent (2024-04-08). "AdaptiveCpp Stdpar: C++ Standard Parallelism Integrated into a SYCL Compiler". Proceedings of the 12th International Workshop on OpenCL and SYCL. IWOCL '24. New York, NY, USA: Association for Computing Machinery. pp. 1–12. doi:10.1145/3648115.3648117. ISBN 979-8-4007-1790-1.
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