Processor supplementary capability
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A processor supplementary capability is a feature that has been added to an existing central processing unit (CPU) design after the initial introduction of that design to the marketplace.
A supplementary capability increases the usefulness of the processor design, allowing it to compete more favorably with competitors and giving consumers a reason to upgrade, while retaining backwards compatibility with the original design.
The CPU supplementary instruction capability does not as a rule apply to 8 or 16 bit CPUs, as many of these CPUs are used mostly as microcontrollers. On modern 32 and 64 bit CPUs the processor supplementary capability does not extend to Floating Point Units (FPUs) or Memory Management Units (MMUs) as these are considered to be fundamental core functionalities. Extensions to the core functionalities of the MMU and FPU may be considered CPU extensions however.
Historical reasoning
[edit]The supplementary instructions feature has always been assumed to mean fixed sets of instructions that are not obligatory across all CPUs in a CPU family. Supplementary instructions will simply not be found on all processors within that family.[1] A programmer who wishes to use a supplementary feature of a CPU is faced with a couple of choices.
Supplemental instruction programming options
- The operating system (kernel) and systems programmer (programs) may choose to design the systems software so that it mandatorily uses that feature and therefore can only be run on the more recent processors that have that feature.
- On the other hand, the system programmer may write or use existing software libraries to determine whether the processor it is running on has a particular feature (or set of instructions).
Should the needed instructions not be there a fall back to a (presumably slower or otherwise less desirable) alternative technique can be initiated or else the program may be set to run with reduced functionality.
- In other cases, an operating system may mimic the new features for older processors, though often with reduced performance.
By using a lowest common denominator strategy (avoiding use of processor supplementary capabilities), programs can be kept portable across all machines of the same architecture.[2]
CPU families affected
[edit]Some popular processor architectures such as x86, 68000, and MIPS have seen many new capabilities introduced over several generations of design.
Some of these capabilities have then seen widespread adoption by programmers, spurring consumer upgrades and making the previous generations of processors obsolete.
x86 capability flags
[edit]| VME | Virtual 8086 mode Enhancement |
| DE | Debugging Extensions |
| PSE | Page Size Extensions |
| TSC | Time Stamp Counter |
| MSR | RDMSR and WRMSR Support |
| PAE | Physical Address Extensions |
| MCE | Machine Check Exception |
| CXS | CMPXCHG8B Instruction (also see Double compare-and-swap and Transactional Synchronization Extensions) |
| APIC | APIC on Chip (also see APIC) |
| MTRR | Memory Type Range Register |
| PGE | PTE Global Bit (also see Page table) |
| MCA | Machine Check Architecture |
| CMOV | Conditional Move and Compare Instructions (also see FCMOV) |
Supplementary Capabilities Not Represented By Flags
[edit]Include (not full list):
Processor Supplementary Instructions
[edit]Processor Supplementary Instructions are instructions that have been implemented on certain processors within a family, but are not present on all processors within a particular family.
IA-32
[edit]The following instructions are considered to be processor supplementary instructions on IA-32 architecture. These instructions were added to later production processors, and are not part of the original IA-32 instruction set. Programs containing these instructions may not operate correctly on all machines in the IA-32 family:
| bswap | byte swap |
| cmov | conditional move |
| cmova | |
| cmovae | |
| cmovb | |
| cmovbe | |
| cmovc | |
| cmove | |
| cmovg | |
| cmovge | |
| cmovl | |
| cmovle | |
| cmovna | |
| cmovnae | |
| cmovnb | |
| cmovnbe | |
| cmovnc | |
| cmovng | |
| cmovnge | |
| cmovnl | |
| cmovnle | |
| cmovno | |
| cmovnp | |
| cmovns | |
| cmovnz | |
| cmovo | |
| cmovp | |
| cmovpe | |
| cmovpo | |
| cmovs | |
| cmovz | |
| cpuid | |
| fcmov | floating point conditional move |
| fcomi | |
| nopl | |
| rdpmc | read performance monitor counts |
| rdtsc | read time stamp counter |
| syscall | |
| sysenter | |
| sysexit | |
| sysret | |
| ud2 | an undefined instruction just for software testing |
| xsave | save processor extended states |
| xrstor | restore processor extended states |
FPU and MMU capability
[edit]The FPU (Floating Point Unit) maths co-processing capability is available on all x86 processors since the 80486DX series. The FPU and MMU instruction sets (for the x86 family) have not been considered supplementary instructions since their introduction due to their importance to core CPU functionality.
See also
[edit]- x86 instruction listings
- CPUID
- Processor Supplementary Instructions For The i686[permanent dead link]