Open JTAG
 | This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these messages)
|
| Original author(s) | Ruben Mileca |
|---|---|
| Repository | opencores |
| Written in | VHDL |
| License | LGPL |
| Website | www |
The Open JTAG project is an open source project released under GNU License.
It is a complete hardware and software JTAG reference design, based on a simple hardware composed by a FTDI FT245 USB front-end and an Altera EPM570 MAX II CPLD. The capabilities of this hardware configuration make the Open JTAG device able to output TCK signals at 24 MHz using macro-instructions sent from the host end.
The scope is to give the community a JTAG device not based on the PC parallel port: Open JTAG uses the USB channel to communicate with the internal CPLD, sending macro-instructions as fast as possible. The complete project (Beta version) is available at OpenCores.org[1] and the Open JTAG project official site.[2]
References
[edit]- ^ OpenCores Open JTAG project
- ^ "Open JTAG official site". Archived from the original on 2010-07-03. Retrieved 2010-07-26.
.svg){kind=logo} | This free and open-source software article is a stub. You can help Wikipedia by expanding it. |