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NCR/32

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NCR/32
General information
Marketed byNCR Corporation
Physical specifications
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The NCR/32 VLSI Processor family was a 32-bit microprocessor architecture and chipset developed by NCR Corporation in the early 1980s. Generally used in minicomputer systems, it was noteworthy for being externally microprogrammable.[1][2]

History

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NCR announced the release of its NCR/32 architecture, comprising an initial four-chip set, in the third quarter of 1982.[3] The Central Processor Chip included an external microcode bus that let a designer create custom instructions for specific applications.

This feature was used to develop microcode that allowed the NCR/32 to emulate NCR's earlier mainframe computers, or an IBM System/370.[4]: 1–5 

The design also enabled high-level languages, such as Prolog and polyFORTH, to be executed directly from custom instructions in the external microcontrol store.[5][6]

Both the NCR/32 processor and some products that used it have been called reduced instruction set computer (RISC) systems, although the description has been debated;[7][8][9] the original Berkeley RISC and Stanford MIPS research programs did not complete until 1984, and avoiding the use of microcode was one of the key RISC design principles.[10][11][12]

NCR used the processor architecture in certain models of their own computer systems, communications peripherals, and at least one board-level product.

Some of the designers of the NCR/32 left NCR for a new company, Celerity Computing, which used the NCR/32 in its own minicomputer designs, running a version of the University of California at Berkeley's Unix Release 4.2.[11][13]

Chipset

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The chipset for the NCR/32 family includes the following devices:

  • NCR/32-000 Central Processor Chip (CPC)
  • NCR/32-010 Address Translation Chip (ATC)
  • NCR/32-020 Extended Arithmetic Chip (EAC)
  • NCR/32-500 System Interface Controller (SIC)
  • NCR/32-580 System Interface Transmitter (SIT)
  • NCR/32-590 System Interface Receiver (SIR)

Features

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The NCR/32-000 CPC was the cornerstone of the architecture; all of the other devices were optional. The CPC consists of 40,000 transistors, and was originally fabricated in a 3 micron NMOS process. The device supports two levels of microcode: vertical microcode, stored in an external 128K-byte Instruction Storage Unit (ISU), and horizontal microcode, stored in an internal Read-only memory (ROM) encoding 179 operations in a set of 95-bit wide words. The CPC accesses the ISU over a 16-bit wide Instruction Storage Unit Bus (ISUBUS), feeding a 3-stage microinstruction pipeline. Internally, the CPC has a 32-bit wide Arithmetic Logic Unit (ALU), and 16 32-bit general purpose registers. The processor can address up to 4 GB of direct virtual memory, and 16 MB of direct real memory over a 32-bit wide Processor Memory Bus (PMBUS). The base clock frequency of the CPC is 13.3 MHz. With its two-phase, non-overlapping clock, each machine cycle takes two "ticks", yielding a cycle time of 150 nanoseconds (nS). 90% of the CPC's microinstructions complete in a single cycle.[1][4][14]

A revised version of the CPC was released later, with device geometry reduced from 3 to 2 microns[15] Cycle time on higher-performance NCR 10000 systems was down to 110 nS.[16]

The NCR/32-010 ATC provides advanced memory management services such as address translation, access protection, memory-refresh control, and error-checking and correction (ECC). It contains sixteen translation registers which handle mapping of 32-bit or 24-bit virtual addresses into 24-bit physical addresses, with page sizes of 1K, 2K, or 4K bytes.[4][14]

The NCR/32-020 EAC accelerates the execution of arithmetic operations, performing IBM-compatible single- and double-precision binary and floating-point arithmetic, packed and unpacked decimal storage, and format conversions.[14]

The NCR/32-500 SIC interfaces the PMBUS to slower peripherals and other systems. The NCR/32-580 SIT and NCR/32-590 SIR perform data format conversions. The SIC/SIT/SIR combination can operate in one of two modes: Data Link Control or Local Area Network.[14][1]

Applications

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References

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  1. ^ a b c NCR Microelectronics Short-Form Catalog—1985 (PDF). Dayton, Ohio, U.S.A.: NCR Corporation. 1985.
  2. ^ Bond, John (1 June 1984). "Architectural Advances Spur 32-Bit Micros". Computer Design. pp. 125–136.
  3. ^ Hannum, David L. (December 1983). "microREVIEW". IEEE Micro. Institute of Electrical and Electronics Engineers. pp. 66–68.
  4. ^ a b c NCR/32 General Information (PDF). Dayton, Ohio, U.S.A.: NCR Corporation. 1984.
  5. ^ Fagin, Barry; Patt, Yale; Srini, Vason; Despain, Alvin (December 1985). "Compiling Prolog Into Microcode: A Case Study Using the NCR/32-000". Proceedings of the 18th annual workshop on Microprogramming. MICRO-18. Association for Computing Machinery. pp. 79–88. doi:10.1145/18927.18914.
  6. ^ McBride, Michael L. (January 1984). "Technical Notes — polyFORTH on the NCR/32" (PDF). The Journal of Forth Application and Research. 2 (1): 77–84.
  7. ^ Masters, Clark (18 November 2021). "Oral History of Clark Masters" (PDF). Computer History Museum (Interview). Interviewed by Uday Kapoor. Escondido, California.
  8. ^ a b MacNicol, Gregory (March 1985). "A Risky New Architecture For The Future?" (PDF). Digital Design. pp. 92–98.
  9. ^ Kern, Dr. Ralf (January–February 1989). "Die Mikroprozessor-Story" [The Microprocessor Story] (PDF). Prisma (in German). No. 1. Computerclub Deutschland e.V. pp. 7–12.
  10. ^ a b c "NCR Moves Mid-Range System 10000 Up-Market with Model 85". techmonitor.ai. 2 May 1990.
  11. ^ a b c "Celerity Shuts Up Shop, Shedding 70% of its Workforce". techmonitor.ai. 7 February 1988.
  12. ^ "FPS Japan to Capitalise on its Parent's Acquisition". 27 Sep 1988. Archived from the original on 2021-04-19. Retrieved 2023-08-06.
  13. ^ "Systems & Peripherals — Celerity: 32-bit engineering unit faster than VAX-11". Computerworld. 1984-09-17. p. 69.
  14. ^ a b c d Mateosian, Richard (January 1984). "1984, the Year of the 32-bit Microprocessor" (PDF). Byte. Vol. 9, no. 1. pp. 134–150.
  15. ^ a b c d Boucher, Henri. Catalogue informatique de Henri Boucher (PDF). Vol. C.
  16. ^ "System 10000 Model 65, Model 75 and Model 85". NCR Products and Systems Pocket Digest (PDF). NCR Corporation. January 1991. pp. 51–55.
  17. ^ "Modell 9300 bietet eine maximale Hauptspeicherkapazität von 4 MB: NCR-Computer mit neuem 32-Bit-Chip" [Model 9300 offers a maximum memory capacity of 4 MB: NCR computer with new 32-bit chip]. www.computerwoche.de (in German). 1 April 1983.
  18. ^ "NCR Marries Its Tower Unix Boxes With Fault-Tolerant 9800". techmonitor.ai. 16 September 1987.
  19. ^ Allison, Andrew (May 1987). "Multiprocessors Boost System Power" (PDF). Mini-Micro Systems. Vol. XX, no. 5. Cahners. pp. 105–117.
  20. ^ "New Products — NCR claims seamless PC integration and transparent networking for new System 10000" (PDF). Computer. The Institute of Electrical and Electronics Engineers. May 1988. p. 94.
  21. ^ Bozman, Jean S. (7 March 1988). "NCR to show next mini line". Computerworld. Vol. XXII, no. 10. p. 1.
  22. ^ "NCR Integrates Mid-Range NCR 10000 With MS-DOS Computing". techmonitor.ai. 14 March 1988.
  23. ^ "Systems & Peripherals — NCR adds 32-bit board-level processor". Computerworld. Vol. XVII, no. 50. 10 December 1984. p. 105.
  24. ^ Dix, John (4 March 1985). "NCR Comten rolls out processor, tools". Computerworld. Vol. XIX, no. 9. pp. 77, 78.
  25. ^ "Microbytes — Nanobytes" (PDF). Byte. April 1984. p. 10.
  26. ^ "Honeywell-NCR". The New York Times. 8 February 1984. p. D-4.
  27. ^ "Company Profiles — 15 Honeywell Inc" (PDF). Datamation. 1 June 1985. p. 70.

Further reading

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