List of x86 virtualization instructions

Instruction set extensions that have been added to the x86 instruction set in order to support hardware virtualization. These extensions provide instructions for entering and leaving a virtualized execution context and for loading virtual-machine control structures (VMCSs), which hold the state of the guest and host, along with fields which control processor behavior within the virtual machine.

AMD-V instructions

Instruction	Opcode	Instruction Description	Used by	Added in

Basic SVM (Secure Virtual Machine) instructions^[1]
`INVLPGA rAX,ECX`^[a]	`0F 01 DF`	Invalidate TLB mappings for the virtual page specified in rAX and the ASID (Address Space IDentifier) specified in ECX.	VMM	K8^[b]
`VMRUN rAX`^[a]	`0F 01 D8`	Run virtual machine managed by the VMCB (Virtual Machine Control Block) specified by physical address in rAX.	VMM
`VMLOAD rAX`^[a]	`0F 01 DA`	Load a specific subset of processor state from the VMCB specified by the physical address in the rAX register.^[c]	Usually the VMM^[d]
`VMSAVE rAX`^[a]	`0F 01 DB`	Save a specific subset of processor state to the VMCB specified by the physical address in the rAX register.^[c]	Usually the VMM^[d]
`STGI`	`0F 01 DC`	Set GIF (Global Interrupt Flag).	Usually the VMM^[e]
`CLGI`	`0F 01 DD`	Clear GIF.	Usually the VMM^[e]
`VMMCALL`	`NFx 0F 01 D9`	Call to VM monitor from guest by causing a VMEXIT.	Guest
`SKINIT EAX`	`0F 01 DE`	Secure Init and Jump with Attestation. Initializes CPU to known state, designates a 64 Kbyte memory area specified by EAX as an SLB ("Secure Loader Block"), submits a copy of the memory area to the system TPM for validation using a digital signature, then jumps into the SLB.	VMM	Turion "Lion",^[2] Opteron "Shanghai", Phenom II
Secure Encrypted Virtualization (SEV): Encrypted State (SEV-ES) instructions
`VMGEXIT`	`F2/F3 0F 01 D9`	SEV-ES Exit to VMM. Explicit communication with the VMM for SEV-ES VMs.^[f]	Guest	Zen 1
Secure Nested Paging (SEV-SNP): Reverse-Map Table (RMP) instructions
`PSMASH`	`F3 0F 01 FF`	Page Smash: expands a 2MB-page RMP entry into a corresponding set of contiguous 4KB-page RMP entries. The 2 MB page's system physical address is specified in the RAX register.	VMM	Zen 3
`RMPUPDATE`	`F2 0F 01 FE`	Write a new RMP entry. The system physical address of a page whose RMP entry is modified is specified in the RAX register. The RCX register provides the effective address of a 16-byte data structure which contains the new RMP state.	VMM
`PVALIDATE`	`F2 0F 01 FF`	Validate or rescind validation of a guest page's RMP entry. The guest virtual address is specified in the register operand rAX.^[a]	Guest
`RMPADJUST`	`F3 0F 01 FE`	Adjust RMP permissions for a guest page. The guest virtual address is specified in the RAX register. The page size is specified in RCX[0]. The target VMPL (Virtual Machine Privilege Level) and its permissions are specified in the RDX register.	Guest
`RMPQUERY`	`F3 0F 01 FD`	Reads an RMP permission mask for a guest page. The guest virtual address is specified in the RAX register. The target VMPL is specified in RDX[7:0]. RMP permissions for the specified VMPL are returned in RDX[63:8] and the RCX register.	Guest	Zen 4
`RMPREAD`	`F2 0F 01 FD`	Read an RMP entry. The system physical address of the page whose RMP entry is to be read is specified in the RAX register. The RCX register provides the effective address of a 16-byte data structure that the RMP entry will be written to.	VMM	(Zen 5)

^ ^a ^b ^c ^d ^e For the rAX argument to the VMRUN, VMLOAD, VMSAVE, INVLPGA and PVALIDATE instructions, the choice of AX/EAX/RAX depends on address-size, which can be overridden with the 67h prefix.
^ Support for AMD-V was added in stepping F of the AMD K8, and is not available on earlier steppings.
^ ^a ^b The VMRUN instruction will load only a limited subset of CPU state - VMLOAD should be run before VMRUN to load additional state.
Similarly, #VMEXIT will store only a limited amount of guest state to the VMCB, and VMSAVE is needed to store additional state.
For simple intercept conditions where the VMM doesn't need to make use of the state items handled by VMSAVE/VMLOAD, the VMM may improve performance by abstaining from performing VMSAVE/VMLOAD before re-entering the virtual machine with VMRUN.
^ On CPUs that support VMLOAD/VMSAVE virtualization (Excavator and later), the VMLOAD and VMSAVE instructions can be executed in guest mode as well.
^ On CPUs that support Virtual GIF (Excavator and later), the STGI and CLGI instructions can be executed in guest mode as well.
^ VMGEXIT is executed as VMMCALL if not executed by a SEV-ES guest.

Intel VT-x instructions

Intel virtualization instructions. VT-x is also supported on some processors from VIA and Zhaoxin.

Instruction	Opcode	Instruction Description	Used by^[a]	Added in

Basic VMX (Virtual Machine Extensions) instructions
`VMXON m64`^[b]	`F3 0F C7 /6`	Enter VMX Operation – enters hardware supported virtualisation environment.^[c]	VMM	Prescott 2M, Yonah, Centerton, Nano 3000
`VMXOFF`	`NP 0F 01 C4`	Leave VMX Operation – stops hardware supported virtualisation environment.
`VMPTRLD m64`^[b]	`NP 0F C7 /6`	Load pointer to Virtual-Machine Control Structure (VMCS) from memory and mark it valid.
`VMPTRST m64`^[b]	`NP 0F C7 /7`	Store pointer to current VMCS to memory.
`VMCLEAR m64`^[b]	`66 0F C7 /6`	Flush VMCS data from CPU to VMCS region in memory. If the specified VMCS is the current VMCS, then the current-VMCS is marked as invalid.
`VMLAUNCH`	`NP 0F 01 C2`	Launch virtual machine managed by current VMCS.
`VMRESUME`	`NP 0F 01 C3`	Resume virtual machine managed by current VMCS.
`VMREAD r/m,reg`	`NP 0F 78 /r`	Read a specified field from the current-VMCS. The `reg` argument specifies which field to read – the result is stored to `r/m`.	Usually the VMM^[d]
`VMWRITE reg,r/m`	`NP 0F 79 /r`	Write to specified field of current-VMCS. The `reg` argument specifies which field to write, and the r/m argument provides the data item to write to the field.	Usually the VMM^[d]
`VMCALL`	`NP 0F 01 C1`	Call to VM monitor from guest by causing a VMEXIT.	Usually the guest^[e]
Extended Page Tables (EPT) instructions
`INVEPT reg,m128`	`66 0F 38 80 /r`	Invalidates EPT-derived entries in the TLBs and paging-structure caches. The `reg` argument specifies an invalidation type, the memory argument specifies a 128-bit descriptor.^[f]	VMM	Nehalem, Centerton,^[3] ZhangJiang
`INVVPID reg,m128`	`66 0F 38 81 /r`	Invalidates entries in the TLBs and paging-structure caches based on VPID (Virtual Processor ID). The `reg` argument specifies an invalidation type, the memory argument specifies a 128-bit descriptor.^[g]	VMM	Nehalem, Centerton,^[3] ZhangJiang
`VMFUNC`	`NP 0F 01 D4`	Invoke VM function specified in EAX.^[h]	Guest	Haswell, Silvermont, LuJiaZui
Trust Domain Extensions (TDX): Secure Arbitration Mode (SEAM) instructions^[5]
`SEAMOPS`	`66 0F 01 CE`	Invoke SEAM specific operations. Operation to perform is specified in RAX.^[i]	SEAM root	(Sapphire Rapids^[6]), Emerald Rapids^[7]
`SEAMRET`	`66 0F 01 CD`	Return to legacy VMX root operation from SEAM VMX root operation.	SEAM root
`SEAMCALL`	`66 0F 01 CF`	Call to SEAM VMX root operation from legacy VMX root operation.	VMM
`TDCALL`	`66 0F 01 CC`	Call to VM monitor from TD guest by causing a VMEXIT.	TD Guest

^ Executing any of the VT-x VMM instructions while within the VM guest will cause a VMEXIT.
If VMX operation has not been entered through VMXON, then all of the VT-x instructions (except VMXON) will cause #UD.
^ ^a ^b ^c ^d The m64 argument to VMPTRLD, VMPTRST, VMCLEAR and VMXON is a 64-bit physical address.
^ The m64 argument to VMXON is the 64-bit physical address to a "VMXON region", which is a 4Kbyte region that must be 4 Kbyte aligned. This region may be used by the processor to support VMX operation in an implementation-dependent manner and should never be accessed by software until the processor has left VMX operation through the VMXOFF instruction.
^ If "VMCS Shadowing" is enabled (available on Haswell and later), the VMREAD and VMWRITE instructions can be executed by the guest as well.
^ The VMCALL instruction can be executed by the VMM as well – doing so will cause a special SMM VM exit.

^ The invalidation types available for the reg argument of INVEPT are:

Value	Function
1	Single-context invalidation: invalidate all mappings associated with EPT-pointer in bits 63:0 of descriptor.
2	Global invalidation: invalidate all mappings associated with all EPT-pointers.

^ The invalidation types available for the reg argument of INVVPID are:

Value	Function
0	Invalidate mapping for linear address and VPID specified in descriptor. (Unlike `INVLPG`, `INVVPID` will fail when used with non-canonical addresses.^[4])
1	Invalidate all mappings for VPID specified in descriptor.
2	All-contexts invalidation: invalidate all mappings for all VPIDs except VPID 0.
3	Invalidate all mappings for VPID specified in descriptor, except global translations.

^ The functions available for VMFUNC in the EAX register are:

EAX	Function
0	EPTP switching: switch extended page table pointer to one of up to 512 table pointers prepared in advance by the VM host. ECX specifies which one of the 512 pointers to use.
1-63	(Reserved, will cause VMEXIT)
≥64	Invalid, will cause #UD.

^ The operations available for SEAMOPS in the RAX register are:

RAX Operation

0 (CAPABILITIES) Return bitmap of supported SEAMOPS leaves in RAX.

1 (SEAMREPORT) Generate SEAMREPORT structure.

Any unsupported value in RAX will cause a #GP(0) exception.

References

^ AMD, AMD64 Virtualization Codenamed “Pacifica” Technology, publication no. 33407, rev 3.01, May 2005. Archived on Jun 13, 2011.
^ CPU-World, CPUID for AMD Turion 64 X2 RM-75, 2022-03-05. Archived on Apr 19, 2023.
^ Intel, Intel® Atom™ Processor S1200 Product Family for Microserver Datasheet, Volume 1 of 2, order no. 328194-001, dec 2012, page 44
^ Vulners, VMX: intercept issue with INVLPG on non-canonical address, 20 Jan 2016.
^ Intel, Trust Domain CPU Architectural Extensions, order no. 343754-002, may 2021.
^ SecurityWeek, Intel Adds TDX to Confidential Computing Portfolio With Launch of 4th Gen Xeon Processors, 10 jan 2023
^ Intel, What Intel Xeon Processors Support for Intel Trust Domain Extensions (Intel TDX)?, 11 Jun 2024 - indicates general market availability of TDX on Emerald Rapids CPUs but limited availability on Sapphire Rapids CPUs. Archived on 13 Jun 2024.

[svm_opsiz-2] For the rAX argument to the VMRUN, VMLOAD, VMSAVE, INVLPGA and PVALIDATE instructions, the choice of AX/EAX/RAX depends on address-size, which can be overridden with the 67h prefix.

[3] Support for AMD-V was added in stepping F of the AMD K8, and is not available on earlier steppings.

[vmloadstore-4] The VMRUN instruction will load only a limited subset of CPU state - VMLOAD should be run before VMRUN to load additional state.
Similarly, #VMEXIT will store only a limited amount of guest state to the VMCB, and VMSAVE is needed to store additional state.
For simple intercept conditions where the VMM doesn't need to make use of the state items handled by VMSAVE/VMLOAD, the VMM may improve performance by abstaining from performing VMSAVE/VMLOAD before re-entering the virtual machine with VMRUN.

[5] On CPUs that support VMLOAD/VMSAVE virtualization (Excavator and later), the VMLOAD and VMSAVE instructions can be executed in guest mode as well.

[6] On CPUs that support Virtual GIF (Excavator and later), the STGI and CLGI instructions can be executed in guest mode as well.

[8] VMGEXIT is executed as VMMCALL if not executed by a SEV-ES guest.

[9] Executing any of the VT-x VMM instructions while within the VM guest will cause a VMEXIT.
If VMX operation has not been entered through VMXON, then all of the VT-x instructions (except VMXON) will cause #UD.

[vmx_ptr64-10] The m64 argument to VMPTRLD, VMPTRST, VMCLEAR and VMXON is a 64-bit physical address.

[11] The m64 argument to VMXON is the 64-bit physical address to a "VMXON region", which is a 4Kbyte region that must be 4 Kbyte aligned. This region may be used by the processor to support VMX operation in an implementation-dependent manner and should never be accessed by software until the processor has left VMX operation through the VMXOFF instruction.

[12] If "VMCS Shadowing" is enabled (available on Haswell and later), the VMREAD and VMWRITE instructions can be executed by the guest as well.

[13] The VMCALL instruction can be executed by the VMM as well – doing so will cause a special SMM VM exit.

[14] The invalidation types available for the reg argument of INVEPT are:

Value Function

1 Single-context invalidation: invalidate all mappings associated with EPT-pointer in bits 63:0 of descriptor.

2 Global invalidation: invalidate all mappings associated with all EPT-pointers.

[17] The invalidation types available for the reg argument of INVVPID are:

Value Function

0 Invalidate mapping for linear address and VPID specified in descriptor.
(Unlike INVLPG, INVVPID will fail when used with non-canonical addresses.^[4])

1 Invalidate all mappings for VPID specified in descriptor.

2 All-contexts invalidation: invalidate all mappings for all VPIDs except VPID 0.

3 Invalidate all mappings for VPID specified in descriptor, except global translations.

[18] The functions available for VMFUNC in the EAX register are:

EAX Function

0 EPTP switching: switch extended page table pointer to one of up to 512 table pointers prepared in advance by the VM host.
ECX specifies which one of the 512 pointers to use.

1-63 (Reserved, will cause VMEXIT)

≥64 Invalid, will cause #UD.

[20] The operations available for SEAMOPS in the RAX register are:

RAX Operation

0 (CAPABILITIES) Return bitmap of supported SEAMOPS leaves in RAX.

1 (SEAMREPORT) Generate SEAMREPORT structure.

Any unsupported value in RAX will cause a #GP(0) exception.

[1] AMD, AMD64 Virtualization Codenamed “Pacifica” Technology, publication no. 33407, rev 3.01, May 2005. Archived on Jun 13, 2011.

[7] CPU-World, CPUID for AMD Turion 64 X2 RM-75, 2022-03-05. Archived on Apr 19, 2023.

[15] Intel, Intel® Atom™ Processor S1200 Product Family for Microserver Datasheet, Volume 1 of 2, order no. 328194-001, dec 2012, page 44

[16] Vulners, VMX: intercept issue with INVLPG on non-canonical address, 20 Jan 2016.

[19] Intel, Trust Domain CPU Architectural Extensions, order no. 343754-002, may 2021.

[21] SecurityWeek, Intel Adds TDX to Confidential Computing Portfolio With Launch of 4th Gen Xeon Processors, 10 jan 2023

[22] Intel, What Intel Xeon Processors Support for Intel Trust Domain Extensions (Intel TDX)?, 11 Jun 2024 - indicates general market availability of TDX on Emerald Rapids CPUs but limited availability on Sapphire Rapids CPUs. Archived on 13 Jun 2024.

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x86 instruction listings
Part of a series on
Main (integer, system, x87) SIMD (MMX, SSE, AVX, FMA, AMX) Virtualization (VT-x, AMD-V, TDX) Cryptographic (e.g. RDRAND, AES-NI) Discontinued (e.g. 3DNow!, MPX, XOP)
v t e

RAX	Operation
0 (CAPABILITIES)	Return bitmap of supported SEAMOPS leaves in RAX.
1 (SEAMREPORT)	Generate SEAMREPORT structure.