Joel Emer
Joel Emer | |
|---|---|
 Emer in 2003 | |
| Born | March 2, 1954 Chicago, United States |
| Nationality | American |
| Alma mater | Purdue University University of Illinois, Urbana-Champaign |
| Known for | Quantitative approach to processor evaluation, contributions to micro-architecture, Asim simulator |
| Awards | Eckert–Mauchly Award, IEEE Fellow, ACM Fellow |
| Scientific career | |
| Institutions | Currently Nvidia and MIT CSAIL; formerly Intel, Compaq and Digital Equipment Corporation |
| Doctoral advisor | Edward S. Davidson |
Joel S. Emer (born March 2, 1954)[1] is a pioneer in computer performance analysis techniques and a microprocessor architect. He is currently a researcher at Nvidia,[2] and a Professor of the Practice at MIT,[3] and was formerly an Intel Fellow.[4] He was the 2009 recipient of the Eckert–Mauchly Award.[4]
Early life and education
[edit]Born March 2, 1954,[1] he received a bachelor's degree in electrical engineering in 1974 from Purdue University. He received his master's degree in 1975 from Purdue. In 1979, Emer received his Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign[3] under the supervision of Prof. Edward S. Davidson.
Career
[edit]His first job immediately after graduation was at Digital Equipment Corporation where he initially worked on VAX performance evaluation and then on Alpha performance evaluation. As a consequence of his performance evaluation work, he became a pioneer in the quantitative approach to computer architecture.
He contributed a variety of research and advanced development ideas that were incorporated into various VAX and Alpha processor designs,[5] In conjunction with the development and application of various performance analysis techniques.
He worked at Compaq and Digital Equipment Corporation.[3] He subsequently worked at Intel, where he was Director of Microarchitecture Research,[5] out of the Massachusetts Microprocessor Design Center (MMDC).[6] He was named an Intel Fellow in 2001.[6]
He is well known, along with his co-author Douglas W. Clark, for a seminal paper on the quantitative analysis of processor architectures,[7] which was published in 1984 in the 11th International Symposium on Computer Architecture. That paper also contained the result that the VAX-11/780's performance was actually 0.5 MIPS instead of 1 MIPS as was previously claimed by DEC. That result helped popularize what Clark called the iron law of processor performance that related cycles per instruction (CPI), frequency and number of instructions to computer performance.
Emer has also contributed to simultaneous multithreading (SMT),[8] memory dependence prediction via store sets, and soft error analysis, and led the development of the Asim simulator.
He was the 2009 recipient of the Eckert–Mauchly Award,[4] for lifetime contributions in computer architecture.[3] In 2020, Emer was elected as a member into the National Academy of Engineering for quantitative analysis of computer architecture and its application to architectural innovation in commercial microprocessors.
He is currently a researcher at Nvidia,[2] having joined in 2024. He is part of the company's Architecture Research group.[5] He is also a Professor of the Practice at MIT.[3][5]
See also
[edit]References
[edit]- ^ a b "Intel Fellow - Joel S. Emer". Retrieved 20 March 2016.
- ^ a b "Joel Emer". nvidia.
- ^ a b c d e "Joel Emer". MIT.
- ^ a b c "ACM, IEEE-CS Honor Processor Architect Who Bridged Industry-Academic Divide". 14 April 2009. Archived from the original on 30 December 2010.
- ^ a b c d "People: Joel Elmer". Nvidia. Retrieved September 6, 2024.
- ^ a b "Intel Appoints Four New Fellows, Names New Vice President". intel.com. Intel. August 30, 2001. Retrieved September 6, 2024.
- ^ A Characterization of Processor Performance in the VAX-11/780, Joel S. Emer, Douglas W. Clark, 1984, lEEE
- ^ "Multithreading -- Mark Smotherman". Retrieved 20 March 2016.
- Notes
- Emer, Joel S.; Clark, Douglas W. (1984). "A characterization of processor performance in the VAX-11/780". Proceedings of the 11th Annual International Symposium on Computer Architecture. pp. 301–310.
