Bit Rate Reduction

Bit Rate Reduction, or BRR, also called Bit Rate Reduced, is a name given to an audio compression method used on the SPC700 sound coprocessor used in the SNES, as well as the audio processors of the Philips CD-i, the PlayStation, and the Apple Macintosh Quadra series.^[1] The method is a form of ADPCM.

BRR compresses each consecutive sequence of sixteen 16-bit PCM samples into a block of 9 bytes. From most to least significant, the first byte of each block consists of four bits indicating the range of the block (see below) which controls the size of steps between the 16 possible values such that minute changes can be recorded if the 16 values are closer together but minute changes are lost if the 16 values are far apart, two bits indicating the filter (see below), and two bits of control information for the SPC700. The remaining eight bytes consist of 16 signed 4-bit nibbles which correspond to the 16 samples, packed in a big-endian manner. As 32 bytes of input become 9 bytes of output, the BRR algorithm yields a 3.56:1 compression ratio.

Decompression algorithm

A nibble n in a block with filter $f$ and range $r$ should be decoded into a PCM sample $s_{t}$ using the following second-order linear prediction equation:

s_{t}=2^{r}n+k_{1}s_{t-1}-k_{2}s_{t-2}

Here, $s_{t-1}$ and $s_{t-2}$ are the last-output and next-to-last-output PCM samples, respectively. The filter type $f$ is translated into IIR prediction coefficients $k$ using the following table:

Filter f	k₁	k₂
0	0	0
1	15/16	0
2	61/32	15/16
3	115/64	13/16

These calculations are all done in signed 16.16 fixed-point arithmetic.

Or in words:

Filter 0 linearly decodes the $r$ bit downquantized version of the samples.
Filter 1 adds an $r$ bit downquantized version of the samples to a lowered previous input (delta pack or differential coding).
Filters 2 and 3 add an $r$ bit downquantized version of the samples to the linear extrapolation from the last two samples (2nd order differential coding).

The coefficients of the above filters are specified as slightly less than 1 or 2 in order to realize a leaky integrator that is more resilient to errors in the encoded bitstream. Otherwise, any errors could propagate infinitely, as an impulse response of an ideal integrator is a step function. The denominators are powers of 2 to facilitate implementation with bit shifts as opposed to a more expensive hardware multiplier.

The PlayStation APU and the Philips CD-i CDIC add another set of coefficients to the above and reorders them, for five unique of 8 filters total (these come from the Green Book and Yellow Book specifications):

Filter f	k₁	k₂
0	0	0
1	15/16	0
2	115/64	13/16
3	49/32	55/64
4	61/32	15/16

These calculations are all done in signed 16.16 fixed-point arithmetic.

References

^ "68kMLA".

SPC 700 Documentation
US Patent 4,685,115 [beginnings of system which became BRR]
US Patent 4,783,792 [further development toward BRR]
US Patent 4,797,902 [BRR; example coefficients can be seen on page 21]
US Patent 4,829,522 [BRR with error correction-aware interpolation for reading from a disc medium such as a MiniDisc; the final MiniDisc implementation did not use BRR]
US Patent 5,041,830 [BRR shifting/quantization]
US Patent 5,070,515 [BRR encoding/noise shaping; example coefficients can be seen on page 23]
US Patent 5,086,475 [BRR Looping, pitch/frequency detection for encoding]
US Patent 5,111,530 [Rather specific patent on the workings of the DSP in the SNES and PlayStation APU]
US Patent 5,128,963 [a later patent on the system which became BRR]
US Patent 5,166,981 [Using LPC analysis for assisting in encoding BRR]
US Patent 5,303,374 [Predictive error generator for assisting in encoding BRR; coefficients can be seen on page 6]
US Patent 5,430,241 [BRR Looping, pitch/frequency detection for encoding, similar to 5,086,475]
US Patent 5,519,166 [BRR Looping, pitch/frequency detection for encoding, continuation of 5,430,241]
US Patent 5,978,492 [BRR in the context of CD-XA on Sony PlayStation ]

[1] "68kMLA".

[1]