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R3000

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R3000
DesignerMIPS Computer Systems
Bits32-bit
DesignRISC

The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.

The MIPS 1 instruction set is small compared to those of the contemporary 80x86 and 680x0 architectures, encoding only more commonly used operations and supporting few addressing modes. Combined with its fixed instruction length and only three different types of instruction formats, this simplified instruction decoding and processing. It employed a 5-stage instruction pipeline, enabling execution at a rate approaching one instruction per cycle, unusual for its time.

This MIPS generation supports up to four co-processors. In addition to the CPU core, the R3000 microprocessor includes a Control Processor (CP), which contains a Translation Lookaside Buffer and a Memory Management Unit.[1] The CP works as a coprocessor. Besides the CP, the R3000 can also support an external R3010 numeric coprocessor,[2] along with two other external coprocessors.

The R3000 CPU does not include level 1 cache. Instead, its on-chip cache controller operates external data and instruction caches of up to 256 KB each. It can access both caches during the same clock cycle.

The R3000 found much success and was used by many companies in their workstations and servers. Users included:

The R3000 was a further development of the R2000 with minor improvements including larger TLB and a faster bus to the external caches. The R3000 die contained 115,000 transistors and measured about 75,000 square mils (48 mm2).[7] MIPS was a fabless semiconductor company, so the R3000 was fabricated by MIPS partners including Integrated Device Technology (IDT), LSI Logic, NEC Corporation, Performance Semiconductor, and others. It was fabricated in a 1.2 μm complementary metal–oxide–semiconductor (CMOS) process[1] with two levels of aluminium interconnect.

The R3000 was also used as an embedded microprocessor. When advances in technology rendered it obsolete for high-performance systems, it found continued use in lower-cost designs. Companies such as LSI Logic and Integrated Device Technology developed derivatives of the R3000 specifically for embedded systems.


MIPS R3000A die shot

Derivatives of the R3000 for non-embedded applications include:

  • R3000A - A further development by MIPS introduced in 1989. It operated at clock frequencies up to 40 MHz.
  • PR3400 - Developed by Performance Semiconductor, introduced in May 1991, also at up to 40 MHz. It integrated the Performance Semiconductor PR3000A and PR3010A onto a single die.

Derivatives of the R3000 for embedded applications include:

IDT R3051
IDT R3081
  • CW4003, DCAM-101 - Aimed at digital camera applications, the CW4003 core featured a "multiplier-addition bolt-on" (MABO) unit for accelerated integer arithmetic and a pixel-processing accelerator (PPA) unit accessible via the coprocessor 2 interface. The DCAM-101 combined the CW4003 core with modules interfacing to a camera sensor, display, storage and other peripherals, also incorporating a JPEG compression/decompression unit.[3]
  • PR31500, PR31700 - Microprocessors from Philips Semiconductors used in the Philips Velo handheld PC range. The 75 MHz PR31700 was fabricated in a 350 nm process, delivered in a 208-pin LQFP, it operated at 3.3 V and dissipated only 350 mW.[citation needed]
  • RISController - A family of embedded microprocessors from IDT. Models included the R3041, R3051, R3052, R3071 and R3081. All models included integrated L1 caches. Higher-end models included larger caches and optional MMUs and FPUs. They competed with the intel i960 and AMD 29000.
  • TX3900 - A microcontroller from Toshiba.
  • Mongoose-V - A radiation-hardened and expanded 10–15 MHz CPU for use on spacecraft, it is still in use today in applications such as NASA's New Horizons space probe.

References

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  1. ^ a b Jurij Šilc; Borut Robič; Theo Ungerer (1999). Processor Architecture: From Dataflow to Superscalar and Beyond. Springer-Verlag Berlin Heidelberg. p. 38. ISBN 978-3-540-64798-0.
  2. ^ Rowen, Chris; Johnson, Mark; Ries, Paul (June 1988). "The MIPS R3010 Floating-Point Coprocessor". IEEE Micro. 8 (3). The Institute of Electrical and Electronics Engineers: 53–62. doi:10.1109/40.540. ISSN 0272-1732. S2CID 12859181. Retrieved 24 April 2022.
  3. ^ a b Archide, Reynaldo (March 1998). "A Flexible CPU for Digital Cameras". Byte. pp. 49–50. Retrieved 17 August 2023.
  4. ^ Sharma, Aashish (21 July 2015). "The Original PlayStation CPU is Powering New Horizons". Fossbytes.
  5. ^ Tomson, Iain (14 January 2015). "PlayStation-processor-powered plutonium probe prepares Pluto pics". The Register.
  6. ^ Dockrill, Peter (17 July 2015). "NASA's New Horizon Probe Made It to Pluto With a PlayStation CPU For a Brain". Science Alert.
  7. ^ Michael Slater, ed. (1992). A Guide to RISC microprocessors. Academic Press, Inc. p. 129. ISBN 978-0-12-649140-1.

Further reading

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