Nord-5

Nord-5 was Norsk Data's first 32-bit machine and was claimed to be the first 32-bit minicomputer, subject to various qualifications. It was described in company literature as an "auxiliary computer... monitored by two or more NORD-1 computers", this arrangement comprising the "NORD Integrated Computer System" or NORDIC system. It was arguably this more comprehensive configuration that supported such claims of achieving an industry first with the machine. Its successor, the Nord-50, was itself described as a "special purpose computer" and had a similar reliance on a Nord-10 host computer.

Introduced in 1972, the Nord-5 was categorised in reporting as a "superminicomputer", described retrospectively as a "technological success but a commercial disaster", eventually being superseded by the ND-500 family, announced in 1981. Initially described as a larger version of the Nord-1 to compete with the UNIVAC 1106 and the IBM System/360 Model 44, the machine used a Nord-1 as its front-end console processor, which ran the majority of the operating system. Being designed for "high performance on number crunching", the machine could perform floating-point multiplication in around 1μs and division in around 8μs. The Nord-50 achieved a reported 0.5 million Whetstone instructions per second in benchmarking.

Nord-5 and Nord-50 architecture

The Nord-5 and Nord-50 provided broadly similar CPUs that do not support dedicated input/output instructions, interrupt-related instructions or memory management functions, these being delegated to the Nord-1 and Nord-10 host computer in each case. Each machine's CPU provides three classes of instructions, each supporting a range of data manipulation operations, divided into those performing memory accesses, those operating on internal or external registers, and those combining register values with a constant operand or argument.

The implementation of the Nord-50's CPU used TTL integrated circuits, employing SN7489 64-bit RAM chips for register storage, and the SN74181 arithmetic logic unit. The latter influenced the instruction encoding supported by the CPU, with the 74181's function select input encoding influencing the memory addressing instruction's function code field.

Compared to the Nord-1 and Nord-10 which offered a limited number of 16-bit registers, the Nord-5 and Nord-50 provided many more general-purpose 32-bit registers, and this is reflected in their instruction set, encoding instructions within 32-bit words, as opposed to the 16-bit instruction word of the Nord-1 and Nord-10, and providing more general instructions for load, store and shift operations, as opposed to the register-specific instructions provided by the Nord-1 and Nord-10. Instructions for arithmetic and register transfer operations are more versatile, as opposed to being confined to acting upon specific registers as the equivalent Nord-1 and Nord-10 instructions do. Double-precision floating-point arithmetic is also a notable benefit of the Nord-5 and Nord-50, meriting additional instructions.

Registers

The CPU in the Nord-5 and Nord-50 provides 64 general registers, 32 bits in size, denoted GR_0..63. Floating-point arithmetic being a core feature of each system, floating-point operations also use these registers. Here, the Nord-5 and Nord-50 diverge in support for floating-point representations, with the Nord-5 only supporting a 64-bit representation with a 52-bit mantissa and 11-bit exponent, whereas the Nord-50 supports 32- and 64-bit representations, with the latter featuring a 55-bit mantissa and 9-bit exponent.

Nord-5/Nord-50 general register aliases

31 ... 00 31 ... 00 Base Register Index Register Floating Register Modification register Floating Register (64-bit) BR0..15 XR0..15 FR0..15 MR0..15 GR0 GR16 FR0 / FDR0 ... ... ... GR15 GR31 FR15 / FDR15 GR32 GR48 FR32 / FDR32 ... ... ... GR47 GR63 FR47 / FDR47 Nord-50 designations are italicised

Since 64-bit values require pairs of 32-bit general registers, the Nord-5 maps each floating register from FR_0..15 to a register from GR_0..15 for the most significant word of the 64-bit representation, pairing that register with one from GR_16..31 for the least significant word. Similarly, FR_32..47 pairs registers from GR_32..47 with those from GR_48..63. This arrangement is continued in the Nord-50 for double-precision floating registers, denoted FDR_0..15,32..47, with single-precision floating registers FR_0..15,32..47 corresponding to GR_0..15,32..47, thus employing only one of the registers in the pairs allocated to double-precision floating registers

The first sixteen general registers are more versatile in that they may be used in the base register or index register role in memory access instructions, thus providing base registers BR_0..15 and index registers XR_0..15. The second sixteen general registers also assume a special role as modification registers under certain circumstances, with MR_0..15 corresponding to GR_16..31. As in other processor architectures, the zero register GR₀ is wired to a value of zero, and this affects all interpretations of the register (as BR₀, FR₀, XR₀ and MR₀).

Special registers dedicated to particular roles include an overflow register (OR) applicable to multiplication and a remainder register (RR) applicable to division. The program counter register (P) holds the address of the instruction being read from memory, and the instruction register (IR) contains the currently executed instruction.

Instruction set

Memory reference instructions involve the computation of an effective memory address and access to this computed location. Such instructions can involve direct or indirect addressing. Direct addressing instructions also involve the execution of an indicated function, utilising the effective address and an indicated register.

Memory reference instruction (direct and indirect)

Bit
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I = 0	X (index)				B (base)				FC (function code)					R/F/FD (register designator)						D (displacement)
I = 1	X (index)				B (base)				0			D (displacement)

In both forms, the effective address is computed using the indicated base and index registers, adding the displacement value:

Ea = R_B + R_X + D

With the I field unset or clear, a direct addressing instruction executes a function indicated by the FC field, utilising the effective address together with a register indicated by the register designator field. Each of the functions provides the basis of a specific individual instruction and include the following examples:

Instructions	Operations
LDR, STR, XMR	Transfers between registers and memory (load, store, exchange)
LDF, STF (Nord-5) LDD, STD (Nord-50)	Transfers of double-precision floating-point values between registers and pairs of memory words (load, store)
ADD, ADM, AND, DIV, MPY, SUB	Arithmetic and logical operations whose results are placed in registers or memory
FAD, FDV, FMU, FSB	Single-precision (Nord-50) or double-precision (Nord-5) floating-point arithmetic, updating registers
FADD, FDVD, FMUD, FSBD	Double-precision (Nord-50) floating-point arithmetic, updating registers
JRF, JRN, JRP, JRZ	Conditional jump operations testing register values, jumping to the effective address
JFM, JNM, JPM, JZM	Conditional jump operations testing modified register values, jumping to the effective address
RTJ	Jump, storing the return address in a register

More unusual operations include conditional skip operations (such as CRD, CRE, CRG, CRL) comparing register values with values retrieved from the effective address, skipping the next instruction in the stream where the condition is satisfied. Remote execution (EXC) involves the execution of an instruction retrieved from the effective address or even the execution of the computed address value itself, interpreted as an instruction.

With the I field set, an indirect addressing instruction occurs, incorporating a potentially greater displacement value in the computation of the effective address. However, no function is involved. Instead, the 32-bit word at the computed effective address location is then obtained to provide another memory reference instruction encoding the details of a new effective address. Thus, an instruction is effectively loaded from outside the regular instruction stream and executed, this being similar to the EXC instruction. Where another indirect addressing instruction is obtained, the cycle of obtaining a new effective address repeats, and the chaining of up to 16 indirect references is permitted by the architecture, terminated by a direct reference.

Inter-register instructions involve operations that only use registers. They can be distinguished from memory reference instructions through bits 18 to 22 being left clear, with bit 31 being left clear to distinguish them from argument instructions.

Inter-register instruction

Bit
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	RFC (function code)				RSC (sub-function code)				0					DR/DF/DFD (destination register designator)						SRA/SRAD (source register A designator)						SRB (source register B designator)

The format suggests the general use of two source registers and one result (destination) register. However, some instructions utilise the SRB field to encode constants such as shift magnitudes or bit numbers. A selection of instructions is supported by the functions encoded by this class of instruction, including the following:

Instructions	Operations
RIN, ROUT	Transfers between processor and external registers
SHR, SHD	Arithmetic and logical shift operations on 32-bit and 64-bit values
BCL, BCM, BST	Clear, complement and set operations on an indicated bit
FIX, FLO FIR, FIRD, FIXD, FLOD (Nord-50)	Conversions between integer and floating-point values
FRO, IRO, LRO	Floating-point and integer arithmetic, and logical operations

Conditional skip instructions also appear in this class of instruction, either involving the testing of individual bits (BSO, BSZ) or performing floating-point and integer arithmetic followed by an indicated comparison operation with zero (FRS, IRS), with the outcome determining whether the next instruction will be skipped. A peculiarity is the monitor call (STOP) instruction which employs zero in the function-related fields, employing bits 0 to 17 as the function code in the Nord-1 or Nord-10 monitor program.

Argument instructions involve operations that apply constant values encoded in the instruction to a register value, updating the register. They can be distinguished from memory reference instructions through bits 18 to 22 being left clear, with bit 31 being left set to distinguish them from inter-register instructions.

Argument instruction

Bit
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	AFC (function code)		DR (destination register)						0					ASF (sub-function code)		A (argument)

This class of instructions is limited to three kinds of "direct" instructions, performing simple arithmetic (DAR), logical operations (DLR), or a conditional skip operation involving the operands and a complement operation (DSK).