Deutsch: Schematische Darstellung der Umsetzung von linearen in physische Adressen bei x86-kompatiblen CPUs im 32-Bit Protected Mode. Seitengröße: 4 MiByte, kein PAE.
English: Schematic drawing of translation of linear to physical addresses in 32 bit protected mode. Page size: 4 MiByte, no PAE
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{{Information |Description={{de|Schematische Darstellung der Umsetzung von linearen in physische Adressen bei x86-kompatiblen CPUs im 32-Bit Protected Mode. Seitengröße: 4 MiByte, kein PAE.}} {{en|Schematic drawing of translation of linear to physical a