File:SR (NAND) Flip-flop.svg

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Summary

DescriptionSR (NAND) Flip-flop.svg	Gate-level Diagram of a NAND-gate SR Flip-flop
Date	17 June 2006
Source	Own Drawing in Inkscape 0.43
Author	jjbeard
Permission (Reusing this file)	PD
Other versions	Unified series of flip-flop symbols SR Asynchronous latch Inverted SR Asynchronous latch SR latch with enable D-type transparent latch Differential D-type Latch SR Synchronous flip-flop Simple D-type flip-flop D-type flip-flop with asynchronous set/reset T-type flip-flop Simple JK flip-flop JK flip-flop with asynchronous set/reset D-type flip-flop with Clock Enable (CE) input

Licensing

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File history

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	Date/Time	Dimensions	User	Comment
current	23:47, 3 May 2009	100 × 100 (7 KB)	Inductiveload	slightly smaller text for consistency
	23:39, 3 May 2009	100 × 100 (7 KB)	Inductiveload	New version, change back to text, make slightly larger for better visibility at 100%
	22:34, 17 June 2006	100 × 100 (9 KB)	Jjbeard	{{Information \|Description=Gate-level Diagram of a NAND-gate SR Flip-flop \|Source=Own Drawing in Inkscape 0.43 \|Date=17/06/06 \|Author=jjbeard \|Permission=PD \|other_versions= }} [[Category