File:DEC MicroVAX II CPU KA630-AA M7606.jpg
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Summary
DescriptionDEC MicroVAX II CPU KA630-AA M7606.jpg |
English: DEC MicroVAX II CPU KA630-AA M7606 CD/Q22-Bus module |
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Source | Own work | |||
Author | Phiarc | |||
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Annotations InfoField | This image is annotated: View the annotations at Commons |
MicroVAX 78032 (DC333) microprocessor
MicroVAX 78132 (DC337) FPU coprocessor
1 MByte local memory
64 KByte boot and diagnostic ROM
Console SLU (Serial Line Unit) UART (DC319 / DL11-compatible "DLART")
MicroVAX gate array with glue logic
Local memory interconnect data bus (32-bit wide plus 4-bit parity)
CD interconnect (back side) for the local memory address bus
Q-Bus / Q22-Bus (i.e. with a 22-bit address space)
MC146818 CMOS real-time clock (RTC) / time of year (TOY) clock (in DEC terms)
HM6264 8Kx8 SRAM for the Q-Bus Address Map aka Q-Bus scatter-gather map (using 512 byte pages)
When a Q-Bus device does DMA the upper 13 bits of the address (9-21, 0-indexed) are used as the address into this memory, the resulting 16-bit data word has one valid bit and 15 address bits; these become the upper 15 (9-23) address bits in the VAX memory space. Since this uses 512 byte pages (i.e. a 9-bit offset) this works out beautifully to map 22-bit Q-Bus addresses to 24-bit physical VAX addresses.
This performs effectively the function of an w:IOMMU.
See drawing 1.5 in M7606-0-0 (drawing no B-CS-M7606-0-27).
Q-Bus transceivers
DEC 021C (DC021) 19-19015-00 Octal bus transceiver
DS3662N DEC8641 (DC8641) DEC-selected quad trapezoidal bus transceiver
DEC8640 (DC8640) Burned-in quad receiver (E16, for IRQ4:7 lines)
Functional assignments:
1x DC8640 for IRQ lines
3x DC021 for the 22 BDAL lines and BWTBT (one line unused)
4x DC8641 for the remaining bus lines
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Date/Time | Thumbnail | Dimensions | User | Comment | |
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current | 12:43, 17 August 2024 | 7,149 × 6,009 (13.23 MB) | Phiarc | Uploaded own work with UploadWizard |
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